1 //===-- PPCInstPrinter.cpp - Convert PPC MCInst to assembly syntax --------===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This class prints an PPC MCInst to a .s file.
11 //
12 //===----------------------------------------------------------------------===//
13
14 #include "PPCInstPrinter.h"
15 #include "MCTargetDesc/PPCMCTargetDesc.h"
16 #include "MCTargetDesc/PPCPredicates.h"
17 #include "PPCInstrInfo.h"
18 #include "llvm/CodeGen/TargetOpcodes.h"
19 #include "llvm/MC/MCExpr.h"
20 #include "llvm/MC/MCInst.h"
21 #include "llvm/MC/MCInstrInfo.h"
22 #include "llvm/MC/MCRegisterInfo.h"
23 #include "llvm/MC/MCSubtargetInfo.h"
24 #include "llvm/MC/MCSymbol.h"
25 #include "llvm/Support/CommandLine.h"
26 #include "llvm/Support/raw_ostream.h"
27 using namespace llvm;
28
29 #define DEBUG_TYPE "asm-printer"
30
31 // FIXME: Once the integrated assembler supports full register names, tie this
32 // to the verbose-asm setting.
33 static cl::opt<bool>
34 FullRegNames("ppc-asm-full-reg-names", cl::Hidden, cl::init(false),
35 cl::desc("Use full register names when printing assembly"));
36
37 // Useful for testing purposes. Prints vs{31-63} as v{0-31} respectively.
38 static cl::opt<bool>
39 ShowVSRNumsAsVR("ppc-vsr-nums-as-vr", cl::Hidden, cl::init(false),
40 cl::desc("Prints full register names with vs{31-63} as v{0-31}"));
41
42 // Prints full register names with percent symbol.
43 static cl::opt<bool>
44 FullRegNamesWithPercent("ppc-reg-with-percent-prefix", cl::Hidden,
45 cl::init(false),
46 cl::desc("Prints full register names with percent"));
47
48 #define PRINT_ALIAS_INSTR
49 #include "PPCGenAsmWriter.inc"
50
printRegName(raw_ostream & OS,unsigned RegNo) const51 void PPCInstPrinter::printRegName(raw_ostream &OS, unsigned RegNo) const {
52 const char *RegName = getRegisterName(RegNo);
53 if (RegName[0] == 'q' /* QPX */) {
54 // The system toolchain on the BG/Q does not understand QPX register names
55 // in .cfi_* directives, so print the name of the floating-point
56 // subregister instead.
57 std::string RN(RegName);
58
59 RN[0] = 'f';
60 OS << RN;
61
62 return;
63 }
64
65 OS << RegName;
66 }
67
printInst(const MCInst * MI,raw_ostream & O,StringRef Annot,const MCSubtargetInfo & STI)68 void PPCInstPrinter::printInst(const MCInst *MI, raw_ostream &O,
69 StringRef Annot, const MCSubtargetInfo &STI) {
70 // Check for slwi/srwi mnemonics.
71 if (MI->getOpcode() == PPC::RLWINM) {
72 unsigned char SH = MI->getOperand(2).getImm();
73 unsigned char MB = MI->getOperand(3).getImm();
74 unsigned char ME = MI->getOperand(4).getImm();
75 bool useSubstituteMnemonic = false;
76 if (SH <= 31 && MB == 0 && ME == (31-SH)) {
77 O << "\tslwi "; useSubstituteMnemonic = true;
78 }
79 if (SH <= 31 && MB == (32-SH) && ME == 31) {
80 O << "\tsrwi "; useSubstituteMnemonic = true;
81 SH = 32-SH;
82 }
83 if (useSubstituteMnemonic) {
84 printOperand(MI, 0, O);
85 O << ", ";
86 printOperand(MI, 1, O);
87 O << ", " << (unsigned int)SH;
88
89 printAnnotation(O, Annot);
90 return;
91 }
92 }
93
94 if ((MI->getOpcode() == PPC::OR || MI->getOpcode() == PPC::OR8) &&
95 MI->getOperand(1).getReg() == MI->getOperand(2).getReg()) {
96 O << "\tmr ";
97 printOperand(MI, 0, O);
98 O << ", ";
99 printOperand(MI, 1, O);
100 printAnnotation(O, Annot);
101 return;
102 }
103
104 if (MI->getOpcode() == PPC::RLDICR ||
105 MI->getOpcode() == PPC::RLDICR_32) {
106 unsigned char SH = MI->getOperand(2).getImm();
107 unsigned char ME = MI->getOperand(3).getImm();
108 // rldicr RA, RS, SH, 63-SH == sldi RA, RS, SH
109 if (63-SH == ME) {
110 O << "\tsldi ";
111 printOperand(MI, 0, O);
112 O << ", ";
113 printOperand(MI, 1, O);
114 O << ", " << (unsigned int)SH;
115 printAnnotation(O, Annot);
116 return;
117 }
118 }
119
120 // dcbt[st] is printed manually here because:
121 // 1. The assembly syntax is different between embedded and server targets
122 // 2. We must print the short mnemonics for TH == 0 because the
123 // embedded/server syntax default will not be stable across assemblers
124 // The syntax for dcbt is:
125 // dcbt ra, rb, th [server]
126 // dcbt th, ra, rb [embedded]
127 // where th can be omitted when it is 0. dcbtst is the same.
128 if (MI->getOpcode() == PPC::DCBT || MI->getOpcode() == PPC::DCBTST) {
129 unsigned char TH = MI->getOperand(0).getImm();
130 O << "\tdcbt";
131 if (MI->getOpcode() == PPC::DCBTST)
132 O << "st";
133 if (TH == 16)
134 O << "t";
135 O << " ";
136
137 bool IsBookE = STI.getFeatureBits()[PPC::FeatureBookE];
138 if (IsBookE && TH != 0 && TH != 16)
139 O << (unsigned int) TH << ", ";
140
141 printOperand(MI, 1, O);
142 O << ", ";
143 printOperand(MI, 2, O);
144
145 if (!IsBookE && TH != 0 && TH != 16)
146 O << ", " << (unsigned int) TH;
147
148 printAnnotation(O, Annot);
149 return;
150 }
151
152 if (MI->getOpcode() == PPC::DCBF) {
153 unsigned char L = MI->getOperand(0).getImm();
154 if (!L || L == 1 || L == 3) {
155 O << "\tdcbf";
156 if (L == 1 || L == 3)
157 O << "l";
158 if (L == 3)
159 O << "p";
160 O << " ";
161
162 printOperand(MI, 1, O);
163 O << ", ";
164 printOperand(MI, 2, O);
165
166 printAnnotation(O, Annot);
167 return;
168 }
169 }
170
171 if (!printAliasInstr(MI, O))
172 printInstruction(MI, O);
173 printAnnotation(O, Annot);
174 }
175
176
printPredicateOperand(const MCInst * MI,unsigned OpNo,raw_ostream & O,const char * Modifier)177 void PPCInstPrinter::printPredicateOperand(const MCInst *MI, unsigned OpNo,
178 raw_ostream &O,
179 const char *Modifier) {
180 unsigned Code = MI->getOperand(OpNo).getImm();
181
182 if (StringRef(Modifier) == "cc") {
183 switch ((PPC::Predicate)Code) {
184 case PPC::PRED_LT_MINUS:
185 case PPC::PRED_LT_PLUS:
186 case PPC::PRED_LT:
187 O << "lt";
188 return;
189 case PPC::PRED_LE_MINUS:
190 case PPC::PRED_LE_PLUS:
191 case PPC::PRED_LE:
192 O << "le";
193 return;
194 case PPC::PRED_EQ_MINUS:
195 case PPC::PRED_EQ_PLUS:
196 case PPC::PRED_EQ:
197 O << "eq";
198 return;
199 case PPC::PRED_GE_MINUS:
200 case PPC::PRED_GE_PLUS:
201 case PPC::PRED_GE:
202 O << "ge";
203 return;
204 case PPC::PRED_GT_MINUS:
205 case PPC::PRED_GT_PLUS:
206 case PPC::PRED_GT:
207 O << "gt";
208 return;
209 case PPC::PRED_NE_MINUS:
210 case PPC::PRED_NE_PLUS:
211 case PPC::PRED_NE:
212 O << "ne";
213 return;
214 case PPC::PRED_UN_MINUS:
215 case PPC::PRED_UN_PLUS:
216 case PPC::PRED_UN:
217 O << "un";
218 return;
219 case PPC::PRED_NU_MINUS:
220 case PPC::PRED_NU_PLUS:
221 case PPC::PRED_NU:
222 O << "nu";
223 return;
224 case PPC::PRED_BIT_SET:
225 case PPC::PRED_BIT_UNSET:
226 llvm_unreachable("Invalid use of bit predicate code");
227 }
228 llvm_unreachable("Invalid predicate code");
229 }
230
231 if (StringRef(Modifier) == "pm") {
232 switch ((PPC::Predicate)Code) {
233 case PPC::PRED_LT:
234 case PPC::PRED_LE:
235 case PPC::PRED_EQ:
236 case PPC::PRED_GE:
237 case PPC::PRED_GT:
238 case PPC::PRED_NE:
239 case PPC::PRED_UN:
240 case PPC::PRED_NU:
241 return;
242 case PPC::PRED_LT_MINUS:
243 case PPC::PRED_LE_MINUS:
244 case PPC::PRED_EQ_MINUS:
245 case PPC::PRED_GE_MINUS:
246 case PPC::PRED_GT_MINUS:
247 case PPC::PRED_NE_MINUS:
248 case PPC::PRED_UN_MINUS:
249 case PPC::PRED_NU_MINUS:
250 O << "-";
251 return;
252 case PPC::PRED_LT_PLUS:
253 case PPC::PRED_LE_PLUS:
254 case PPC::PRED_EQ_PLUS:
255 case PPC::PRED_GE_PLUS:
256 case PPC::PRED_GT_PLUS:
257 case PPC::PRED_NE_PLUS:
258 case PPC::PRED_UN_PLUS:
259 case PPC::PRED_NU_PLUS:
260 O << "+";
261 return;
262 case PPC::PRED_BIT_SET:
263 case PPC::PRED_BIT_UNSET:
264 llvm_unreachable("Invalid use of bit predicate code");
265 }
266 llvm_unreachable("Invalid predicate code");
267 }
268
269 assert(StringRef(Modifier) == "reg" &&
270 "Need to specify 'cc', 'pm' or 'reg' as predicate op modifier!");
271 printOperand(MI, OpNo+1, O);
272 }
273
printATBitsAsHint(const MCInst * MI,unsigned OpNo,raw_ostream & O)274 void PPCInstPrinter::printATBitsAsHint(const MCInst *MI, unsigned OpNo,
275 raw_ostream &O) {
276 unsigned Code = MI->getOperand(OpNo).getImm();
277 if (Code == 2)
278 O << "-";
279 else if (Code == 3)
280 O << "+";
281 }
282
printU1ImmOperand(const MCInst * MI,unsigned OpNo,raw_ostream & O)283 void PPCInstPrinter::printU1ImmOperand(const MCInst *MI, unsigned OpNo,
284 raw_ostream &O) {
285 unsigned int Value = MI->getOperand(OpNo).getImm();
286 assert(Value <= 1 && "Invalid u1imm argument!");
287 O << (unsigned int)Value;
288 }
289
printU2ImmOperand(const MCInst * MI,unsigned OpNo,raw_ostream & O)290 void PPCInstPrinter::printU2ImmOperand(const MCInst *MI, unsigned OpNo,
291 raw_ostream &O) {
292 unsigned int Value = MI->getOperand(OpNo).getImm();
293 assert(Value <= 3 && "Invalid u2imm argument!");
294 O << (unsigned int)Value;
295 }
296
printU3ImmOperand(const MCInst * MI,unsigned OpNo,raw_ostream & O)297 void PPCInstPrinter::printU3ImmOperand(const MCInst *MI, unsigned OpNo,
298 raw_ostream &O) {
299 unsigned int Value = MI->getOperand(OpNo).getImm();
300 assert(Value <= 8 && "Invalid u3imm argument!");
301 O << (unsigned int)Value;
302 }
303
printU4ImmOperand(const MCInst * MI,unsigned OpNo,raw_ostream & O)304 void PPCInstPrinter::printU4ImmOperand(const MCInst *MI, unsigned OpNo,
305 raw_ostream &O) {
306 unsigned int Value = MI->getOperand(OpNo).getImm();
307 assert(Value <= 15 && "Invalid u4imm argument!");
308 O << (unsigned int)Value;
309 }
310
printS5ImmOperand(const MCInst * MI,unsigned OpNo,raw_ostream & O)311 void PPCInstPrinter::printS5ImmOperand(const MCInst *MI, unsigned OpNo,
312 raw_ostream &O) {
313 int Value = MI->getOperand(OpNo).getImm();
314 Value = SignExtend32<5>(Value);
315 O << (int)Value;
316 }
317
printU5ImmOperand(const MCInst * MI,unsigned OpNo,raw_ostream & O)318 void PPCInstPrinter::printU5ImmOperand(const MCInst *MI, unsigned OpNo,
319 raw_ostream &O) {
320 unsigned int Value = MI->getOperand(OpNo).getImm();
321 assert(Value <= 31 && "Invalid u5imm argument!");
322 O << (unsigned int)Value;
323 }
324
printU6ImmOperand(const MCInst * MI,unsigned OpNo,raw_ostream & O)325 void PPCInstPrinter::printU6ImmOperand(const MCInst *MI, unsigned OpNo,
326 raw_ostream &O) {
327 unsigned int Value = MI->getOperand(OpNo).getImm();
328 assert(Value <= 63 && "Invalid u6imm argument!");
329 O << (unsigned int)Value;
330 }
331
printU7ImmOperand(const MCInst * MI,unsigned OpNo,raw_ostream & O)332 void PPCInstPrinter::printU7ImmOperand(const MCInst *MI, unsigned OpNo,
333 raw_ostream &O) {
334 unsigned int Value = MI->getOperand(OpNo).getImm();
335 assert(Value <= 127 && "Invalid u7imm argument!");
336 O << (unsigned int)Value;
337 }
338
339 // Operands of BUILD_VECTOR are signed and we use this to print operands
340 // of XXSPLTIB which are unsigned. So we simply truncate to 8 bits and
341 // print as unsigned.
printU8ImmOperand(const MCInst * MI,unsigned OpNo,raw_ostream & O)342 void PPCInstPrinter::printU8ImmOperand(const MCInst *MI, unsigned OpNo,
343 raw_ostream &O) {
344 unsigned char Value = MI->getOperand(OpNo).getImm();
345 O << (unsigned int)Value;
346 }
347
printU10ImmOperand(const MCInst * MI,unsigned OpNo,raw_ostream & O)348 void PPCInstPrinter::printU10ImmOperand(const MCInst *MI, unsigned OpNo,
349 raw_ostream &O) {
350 unsigned short Value = MI->getOperand(OpNo).getImm();
351 assert(Value <= 1023 && "Invalid u10imm argument!");
352 O << (unsigned short)Value;
353 }
354
printU12ImmOperand(const MCInst * MI,unsigned OpNo,raw_ostream & O)355 void PPCInstPrinter::printU12ImmOperand(const MCInst *MI, unsigned OpNo,
356 raw_ostream &O) {
357 unsigned short Value = MI->getOperand(OpNo).getImm();
358 assert(Value <= 4095 && "Invalid u12imm argument!");
359 O << (unsigned short)Value;
360 }
361
printS16ImmOperand(const MCInst * MI,unsigned OpNo,raw_ostream & O)362 void PPCInstPrinter::printS16ImmOperand(const MCInst *MI, unsigned OpNo,
363 raw_ostream &O) {
364 if (MI->getOperand(OpNo).isImm())
365 O << (short)MI->getOperand(OpNo).getImm();
366 else
367 printOperand(MI, OpNo, O);
368 }
369
printU16ImmOperand(const MCInst * MI,unsigned OpNo,raw_ostream & O)370 void PPCInstPrinter::printU16ImmOperand(const MCInst *MI, unsigned OpNo,
371 raw_ostream &O) {
372 if (MI->getOperand(OpNo).isImm())
373 O << (unsigned short)MI->getOperand(OpNo).getImm();
374 else
375 printOperand(MI, OpNo, O);
376 }
377
printBranchOperand(const MCInst * MI,unsigned OpNo,raw_ostream & O)378 void PPCInstPrinter::printBranchOperand(const MCInst *MI, unsigned OpNo,
379 raw_ostream &O) {
380 if (!MI->getOperand(OpNo).isImm())
381 return printOperand(MI, OpNo, O);
382
383 // Branches can take an immediate operand. This is used by the branch
384 // selection pass to print .+8, an eight byte displacement from the PC.
385 O << ".";
386 int32_t Imm = SignExtend32<32>((unsigned)MI->getOperand(OpNo).getImm() << 2);
387 if (Imm >= 0)
388 O << "+";
389 O << Imm;
390 }
391
printAbsBranchOperand(const MCInst * MI,unsigned OpNo,raw_ostream & O)392 void PPCInstPrinter::printAbsBranchOperand(const MCInst *MI, unsigned OpNo,
393 raw_ostream &O) {
394 if (!MI->getOperand(OpNo).isImm())
395 return printOperand(MI, OpNo, O);
396
397 O << SignExtend32<32>((unsigned)MI->getOperand(OpNo).getImm() << 2);
398 }
399
400
printcrbitm(const MCInst * MI,unsigned OpNo,raw_ostream & O)401 void PPCInstPrinter::printcrbitm(const MCInst *MI, unsigned OpNo,
402 raw_ostream &O) {
403 unsigned CCReg = MI->getOperand(OpNo).getReg();
404 unsigned RegNo;
405 switch (CCReg) {
406 default: llvm_unreachable("Unknown CR register");
407 case PPC::CR0: RegNo = 0; break;
408 case PPC::CR1: RegNo = 1; break;
409 case PPC::CR2: RegNo = 2; break;
410 case PPC::CR3: RegNo = 3; break;
411 case PPC::CR4: RegNo = 4; break;
412 case PPC::CR5: RegNo = 5; break;
413 case PPC::CR6: RegNo = 6; break;
414 case PPC::CR7: RegNo = 7; break;
415 }
416 O << (0x80 >> RegNo);
417 }
418
printMemRegImm(const MCInst * MI,unsigned OpNo,raw_ostream & O)419 void PPCInstPrinter::printMemRegImm(const MCInst *MI, unsigned OpNo,
420 raw_ostream &O) {
421 printS16ImmOperand(MI, OpNo, O);
422 O << '(';
423 if (MI->getOperand(OpNo+1).getReg() == PPC::R0)
424 O << "0";
425 else
426 printOperand(MI, OpNo+1, O);
427 O << ')';
428 }
429
printMemRegReg(const MCInst * MI,unsigned OpNo,raw_ostream & O)430 void PPCInstPrinter::printMemRegReg(const MCInst *MI, unsigned OpNo,
431 raw_ostream &O) {
432 // When used as the base register, r0 reads constant zero rather than
433 // the value contained in the register. For this reason, the darwin
434 // assembler requires that we print r0 as 0 (no r) when used as the base.
435 if (MI->getOperand(OpNo).getReg() == PPC::R0)
436 O << "0";
437 else
438 printOperand(MI, OpNo, O);
439 O << ", ";
440 printOperand(MI, OpNo+1, O);
441 }
442
printTLSCall(const MCInst * MI,unsigned OpNo,raw_ostream & O)443 void PPCInstPrinter::printTLSCall(const MCInst *MI, unsigned OpNo,
444 raw_ostream &O) {
445 // On PPC64, VariantKind is VK_None, but on PPC32, it's VK_PLT, and it must
446 // come at the _end_ of the expression.
447 const MCOperand &Op = MI->getOperand(OpNo);
448 const MCSymbolRefExpr &refExp = cast<MCSymbolRefExpr>(*Op.getExpr());
449 O << refExp.getSymbol().getName();
450 O << '(';
451 printOperand(MI, OpNo+1, O);
452 O << ')';
453 if (refExp.getKind() != MCSymbolRefExpr::VK_None)
454 O << '@' << MCSymbolRefExpr::getVariantKindName(refExp.getKind());
455 }
456
457 /// showRegistersWithPercentPrefix - Check if this register name should be
458 /// printed with a percentage symbol as prefix.
showRegistersWithPercentPrefix(const char * RegName) const459 bool PPCInstPrinter::showRegistersWithPercentPrefix(const char *RegName) const {
460 if (!FullRegNamesWithPercent || TT.isOSDarwin() || TT.getOS() == Triple::AIX)
461 return false;
462
463 switch (RegName[0]) {
464 default:
465 return false;
466 case 'r':
467 case 'f':
468 case 'q':
469 case 'v':
470 case 'c':
471 return true;
472 }
473 }
474
475 /// getVerboseConditionalRegName - This method expands the condition register
476 /// when requested explicitly or targetting Darwin.
getVerboseConditionRegName(unsigned RegNum,unsigned RegEncoding) const477 const char *PPCInstPrinter::getVerboseConditionRegName(unsigned RegNum,
478 unsigned RegEncoding)
479 const {
480 if (!TT.isOSDarwin() && !FullRegNames)
481 return nullptr;
482 if (RegNum < PPC::CR0EQ || RegNum > PPC::CR7UN)
483 return nullptr;
484 const char *CRBits[] = {
485 "lt", "gt", "eq", "un",
486 "4*cr1+lt", "4*cr1+gt", "4*cr1+eq", "4*cr1+un",
487 "4*cr2+lt", "4*cr2+gt", "4*cr2+eq", "4*cr2+un",
488 "4*cr3+lt", "4*cr3+gt", "4*cr3+eq", "4*cr3+un",
489 "4*cr4+lt", "4*cr4+gt", "4*cr4+eq", "4*cr4+un",
490 "4*cr5+lt", "4*cr5+gt", "4*cr5+eq", "4*cr5+un",
491 "4*cr6+lt", "4*cr6+gt", "4*cr6+eq", "4*cr6+un",
492 "4*cr7+lt", "4*cr7+gt", "4*cr7+eq", "4*cr7+un"
493 };
494 return CRBits[RegEncoding];
495 }
496
497 // showRegistersWithPrefix - This method determines whether registers
498 // should be number-only or include the prefix.
showRegistersWithPrefix() const499 bool PPCInstPrinter::showRegistersWithPrefix() const {
500 if (TT.getOS() == Triple::AIX)
501 return false;
502 return TT.isOSDarwin() || FullRegNamesWithPercent || FullRegNames;
503 }
504
printOperand(const MCInst * MI,unsigned OpNo,raw_ostream & O)505 void PPCInstPrinter::printOperand(const MCInst *MI, unsigned OpNo,
506 raw_ostream &O) {
507 const MCOperand &Op = MI->getOperand(OpNo);
508 if (Op.isReg()) {
509 unsigned Reg = Op.getReg();
510 if (!ShowVSRNumsAsVR)
511 Reg = PPCInstrInfo::getRegNumForOperand(MII.get(MI->getOpcode()),
512 Reg, OpNo);
513
514 const char *RegName;
515 RegName = getVerboseConditionRegName(Reg, MRI.getEncodingValue(Reg));
516 if (RegName == nullptr)
517 RegName = getRegisterName(Reg);
518 if (showRegistersWithPercentPrefix(RegName))
519 O << "%";
520 if (!showRegistersWithPrefix())
521 RegName = PPCRegisterInfo::stripRegisterPrefix(RegName);
522
523 O << RegName;
524 return;
525 }
526
527 if (Op.isImm()) {
528 O << Op.getImm();
529 return;
530 }
531
532 assert(Op.isExpr() && "unknown operand kind in printOperand");
533 Op.getExpr()->print(O, &MAI);
534 }
535
536