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Searched refs:getNode (Results 1 – 25 of 170) sorted by relevance

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/freebsd-12.1/contrib/llvm/lib/CodeGen/SelectionDAG/
H A DDAGCombiner.cpp1135 ReplaceLoadWithPromotedLoad(Op.getNode(), NewOp.getNode()); in SExtPromoteOperand()
1150 ReplaceLoadWithPromotedLoad(Op.getNode(), NewOp.getNode()); in ZExtPromoteOperand()
3675 if (LoOpt.getNode() && LoOpt.getNode() != Lo.getNode() && in SimplifyNodeWithTwoResults()
5687 if (LHSMask.getNode() || RHSMask.getNode()) { in MatchRotate()
5710 if (LHSMask.getNode() || RHSMask.getNode()) in MatchRotate()
8619 if (NarrowLoad.getNode() != N0.getNode()) { in visitSIGN_EXTEND()
8879 if (NarrowLoad.getNode() != N0.getNode()) { in visitZERO_EXTEND()
9112 if (NarrowLoad.getNode() != N0.getNode()) { in visitANY_EXTEND()
12474 if (Tmp.getNode() == N.getNode()) in rebuildSetCC()
12524 if (Simp.getNode()) AddToWorklist(Simp.getNode()); in visitBR_CC()
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H A DLegalizeVectorOps.cpp231 SDNode* Node = Op.getNode(); in LegalizeOp()
522 Op = DAG.getNode(Op.getOpcode(), dl, NVT, Operands, Op.getNode()->getFlags()); in Promote()
684 if (Hi.getNode()) in ExpandLoad()
911 return DAG.getNode( in ExpandANY_EXTEND_VECTOR_INREG()
932 return DAG.getNode(ISD::SRA, DL, VT, in ExpandSIGN_EXTEND_VECTOR_INREG()
963 return DAG.getNode(ISD::BITCAST, DL, VT, in ExpandZERO_EXTEND_VECTOR_INREG()
1089 return DAG.UnrollVectorOp(Op.getNode()); in ExpandABS()
1099 return DAG.UnrollVectorOp(Op.getNode()); in ExpandFP_TO_UINT()
1277 SDValue LHSElem = DAG.getNode( in UnrollVSETCC()
1280 SDValue RHSElem = DAG.getNode( in UnrollVSETCC()
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H A DLegalizeIntegerTypes.cpp178 if (Res.getNode()) in PromoteIntegerResult()
365 return DAG.getNode(ISD::SRL, dl, NVT, DAG.getNode(ISD::BSWAP, dl, NVT, Op), in PromoteIntRes_BSWAP()
413 return DAG.getNode( in PromoteIntRes_CTLZ()
1102 if (Res.getNode() == N) in PromoteIntegerOperand()
1620 if (Lo.getNode()) in ExpandIntegerResult()
2296 Lo = DAG.getNode(ISD::ADD, dl, NVT, DAG.getNode(ISD::CTPOP, dl, NVT, Lo), in ExpandIntRes_CTPOP()
2460 Lo = DAG.getNode( in ExpandIntRes_LOAD()
2851 Hi = DAG.getNode( in ExpandIntRes_SIGN_EXTEND()
3279 if (!LoCmp.getNode()) in IntegerExpandSetCCOperands()
3286 if (!HiCmp.getNode()) in IntegerExpandSetCCOperands()
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H A DLegalizeDAG.cpp567 Hi = DAG.getNode( in LegalizeStoreOps()
579 Hi = DAG.getNode( in LegalizeStoreOps()
794 Hi = DAG.getNode( in LegalizeLoadOps()
825 Hi = DAG.getNode( in LegalizeLoadOps()
1313 if (!Ch.getNode()) { in ExpandExtractFromVectorThroughStack()
1910 if (!Value1.getNode()) in ExpandBUILD_VECTOR()
3470 Tmp2 = DAG.getNode( in ExpandNode()
3571 if (Tmp3.getNode()) in ExpandNode()
3664 if (CC.getNode()) { in ExpandNode()
4150 Tmp1 = DAG.getNode( in PromoteNode()
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H A DResourcePriorityQueue.cpp75 const SDNode *ScegN = PredSU->getNode(); in numberRCValPredInSU()
112 const SDNode *ScegN = SuccSU->getNode(); in numberRCValSuccInSU()
239 if (!SU || !SU->getNode()) in isResourceAvailable()
244 if (SU->getNode()->getGluedNode()) in isResourceAvailable()
249 if (SU->getNode()->isMachineOpcode()) in isResourceAvailable()
289 if (SU->getNode() && SU->getNode()->isMachineOpcode()) { in reserveResources()
293 SU->getNode()->getMachineOpcode())); in reserveResources()
321 if (!SU || !SU->getNode() || !SU->getNode()->isMachineOpcode()) in rawRegPressureDelta()
336 if (isa<ConstantSDNode>(Op.getNode())) in rawRegPressureDelta()
355 if (!SU || !SU->getNode() || !SU->getNode()->isMachineOpcode()) in regPressureDelta()
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H A DTargetLowering.cpp277 NewLHS = DAG.getNode( in softenSetCCOperands()
4045 assert((LL.getNode() && LH.getNode() && RL.getNode() && RH.getNode()) || in expandMUL_LOHI()
4046 (!LL.getNode() && !LH.getNode() && !RL.getNode() && !RH.getNode())); in expandMUL_LOHI()
4066 if (!LL.getNode() && !RL.getNode() && in expandMUL_LOHI()
4072 if (!LL.getNode()) in expandMUL_LOHI()
4112 if (!LH.getNode() && !RH.getNode() && in expandMUL_LOHI()
4121 if (!LH.getNode()) in expandMUL_LOHI()
4305 Result = DAG.getNode(ISD::OR, DL, VT, DAG.getNode(ShOpc, DL, VT, Op0, And0), in expandROT()
4589 Op = DAG.getNode(ISD::ADD, dl, VT, DAG.getNode(ISD::AND, dl, VT, Op, Mask33), in expandCTPOP()
4603 DAG.getNode(ISD::SRL, dl, VT, DAG.getNode(ISD::MUL, dl, VT, Op, Mask01), in expandCTPOP()
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H A DLegalizeTypesGeneric.cpp63 Lo = DAG.getNode(ISD::BITCAST, dl, NOutVT, Lo); in ExpandRes_BITCAST()
64 Hi = DAG.getNode(ISD::BITCAST, dl, NOutVT, Hi); in ExpandRes_BITCAST()
75 Lo = DAG.getNode(ISD::BITCAST, dl, NOutVT, Lo); in ExpandRes_BITCAST()
76 Hi = DAG.getNode(ISD::BITCAST, dl, NOutVT, Hi); in ExpandRes_BITCAST()
83 Lo = DAG.getNode(ISD::BITCAST, dl, NOutVT, Lo); in ExpandRes_BITCAST()
84 Hi = DAG.getNode(ISD::BITCAST, dl, NOutVT, Hi); in ExpandRes_BITCAST()
129 Vals.push_back(DAG.getNode( in ExpandRes_BITCAST()
144 Vals.push_back(DAG.getNode( in ExpandRes_BITCAST()
233 SDValue NewVec = DAG.getNode(ISD::BITCAST, dl, in ExpandRes_EXTRACT_VECTOR_ELT()
429 SDValue NewVec = DAG.getNode(ISD::BITCAST, dl, in ExpandOp_INSERT_VECTOR_ELT()
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H A DLegalizeVectorTypes.cpp181 if (R.getNode()) in ScalarizeVectorResult()
329 Op = DAG.getNode( in ScalarizeVecRes_UnaryOp()
355 Op = DAG.getNode( in ScalarizeVecRes_VecInregOp()
393 Cond = DAG.getNode( in ScalarizeVecRes_VSELECT()
495 LHS = DAG.getNode( in ScalarizeVecRes_SETCC()
498 RHS = DAG.getNode( in ScalarizeVecRes_SETCC()
523 if (!Res.getNode()) { in ScalarizeVectorOperand()
868 if (Lo.getNode()) in SplitVectorResult()
1689 if (!Res.getNode()) { in SplitVectorOperand()
2555 if (Res.getNode()) in WidenVectorResult()
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H A DSelectionDAGBuilder.cpp318 return DAG.getNode( in getCopyFromParts()
427 return DAG.getNode( in getCopyFromPartsVector()
461 return DAG.getNode( in getCopyFromPartsVector()
674 Val = DAG.getNode( in getCopyToPartsVector()
734 Ops[i] = DAG.getNode( in getCopyToPartsVector()
1171 if (Val.getNode()) { in resolveDanglingDebugInfo()
1247 if (N.getNode()) { in getNonRegisterValue()
5275 if (N.getNode()) { in visitIntrinsicCall()
5339 if (N.getNode()) { in visitIntrinsicCall()
5855 Res = DAG.getNode( in visitIntrinsicCall()
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/freebsd-12.1/contrib/llvm/lib/Target/AMDGPU/
H A DAMDGPUISelLowering.cpp1499 jq = DAG.getNode(ISD::SRA, DL, VT, jq, in LowerDIVREM24()
2565 E = DAG.getNode(ISD::AND, DL, MVT::i32, E, in LowerFP_TO_FP16()
2569 E = DAG.getNode(ISD::ADD, DL, MVT::i32, E, in LowerFP_TO_FP16()
2940 DCI.AddToWorklist(Lo.getNode()); in splitBinaryBitConstantOpImpl()
2941 DCI.AddToWorklist(Hi.getNode()); in splitBinaryBitConstantOpImpl()
3153 DCI.AddToWorklist(Trunc.getNode()); in performTruncateCombine()
3157 DCI.AddToWorklist(Amt.getNode()); in performTruncateCombine()
3187 SDValue Mul = DAG.getNode(MulOpc, SL, in getMul24()
3261 DCI.AddToWorklist(Mulhi.getNode()); in performMulhsCombine()
3285 DCI.AddToWorklist(Mulhi.getNode()); in performMulhuCombine()
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H A DR600ISelLowering.cpp491 assert((!Result.getNode() || in LowerOperation()
700 Args.push_back(DAG.getNode( in vectorToVerticalVector()
883 return DAG.getNode( in lowerFP_TO_UINT()
893 return DAG.getNode( in lowerFP_TO_SINT()
1983 if (LHS.getOperand(2).getNode() != True.getNode() || in PerformDAGCombine()
1984 LHS.getOperand(3).getNode() != False.getNode() || in PerformDAGCombine()
1985 RHS.getNode() != False.getNode()) { in PerformDAGCombine()
2083 if (!Neg.getNode()) in FoldOperand()
2089 if (!Abs.getNode()) in FoldOperand()
2098 if (!Sel.getNode()) in FoldOperand()
[all …]
/freebsd-12.1/contrib/llvm/lib/Target/Hexagon/
H A DHexagonISelLoweringHVX.cpp290 return DAG.getNode(ISD::SHL, dl, MVT::i32, in convertToByteIndex()
374 if (!SplatV.getNode()) in buildHvxVectorReg()
382 assert(SplatV.getNode()); in buildHvxVectorReg()
422 if (Vec.getNode() != nullptr && T.getNode() != Vec.getNode()) in buildHvxVectorReg()
1056 for (SDValue V : Op.getNode()->ops()) in LowerHvxConcatVectors()
1099 ArrayRef<SDUse> U(Op.getNode()->ops()); in LowerHvxConcatVectors()
1116 for (SDValue V : Op.getNode()->op_values()) { in LowerHvxConcatVectors()
1258 SDValue A = DAG.getNode(ISD::AND, dl, ResTy, in LowerHvxCttz()
1261 return DAG.getNode(ISD::SUB, dl, ResTy, in LowerHvxCttz()
1452 for (SDValue A : Op.getNode()->ops()) { in SplitHvxPairOp()
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H A DHexagonISelDAGToDAG.cpp273 SDNode *C = Ch.getNode(); in tryLoadOfLoadIntrinsic()
301 if (C->getNumOperands() < 4 || Loc.getNode() != C->getOperand(3).getNode()) in tryLoadOfLoadIntrinsic()
1068 ReplaceNode(T0.getNode(), NewShl.getNode()); in ppAddrReorderAddShl()
1144 ReplaceNode(T0.getNode(), NewShl.getNode()); in ppAddrRewriteAndSrl()
1642 assert(A.Value.getNode() && B.Value.getNode()); in Compare()
1888 if ((!isOpcodeHandled(Op0.getNode()) || RootWeights.count(Op0.getNode())) && in balanceSubTree()
1889 (!isOpcodeHandled(Op1.getNode()) || RootWeights.count(Op1.getNode()))) { in balanceSubTree()
1953 if (Child.getNode() != N && RootWeights.count(Child.getNode())) { in balanceSubTree()
2118 if (GA.Value.getNode()) in balanceSubTree()
2149 if ((RootWeights.count(V0.getNode()) && RootWeights[V0.getNode()] == -2) || in balanceSubTree()
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/freebsd-12.1/contrib/llvm/lib/Target/ARM/
H A DARMISelLowering.cpp2161 if (InFlag.getNode()) in LowerCall()
2588 if (Flag.getNode()) in LowerReturn()
4130 if (True.getNode() && False.getNode()) { in LowerSELECT()
8157 if (Res.getNode()) in ReplaceNodeResults()
9788 if (!IsVUZPShuffleNode(N0.getNode()) || N0.getNode() != N1.getNode() || in AddCombineToVPADD()
9826 if (!IsVUZPShuffleNode(N00.getNode()) || N00.getNode() != N10.getNode() || in AddCombineVUZPToVPADDL()
10092 if (AddcSubcOp0.getNode() == AddcSubcOp1.getNode()) in AddCombineTo64bitMLAL()
10113 if (AddeSubeOp0.getNode() == AddeSubeOp1.getNode()) in AddCombineTo64bitMLAL()
10865 if ((SRL.getOperand(0).getNode() != SHL.getOperand(0).getNode()) || in PerformORCombineToSMULWBT()
11335 Op0.getNode() == Op1.getNode() && in PerformVMOVDRRCombine()
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/freebsd-12.1/contrib/llvm/lib/Target/XCore/
H A DXCoreISelLowering.cpp565 SDValue Lo(Hi.getNode(), 1); in LowerSMUL_LOHI()
582 SDValue Lo(Hi.getNode(), 1); in LowerUMUL_LOHI()
679 SDValue Lo(Hi.getNode(), 1); in TryExpandADDWithMul()
687 SDValue Lo(Hi.getNode(), 1); in TryExpandADDWithMul()
698 SDValue Lo(Hi.getNode(), 1); in TryExpandADDWithMul()
739 SDValue Carry(Lo.getNode(), 1); in ExpandADDSUB()
743 SDValue Ignored(Hi.getNode(), 1); in ExpandADDSUB()
753 SDNode *Node = Op.getNode(); in LowerVAARG()
1209 if (InFlag.getNode()) in LowerCCCCallTo()
1506 if (Flag.getNode()) in LowerReturn()
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/freebsd-12.1/contrib/llvm/lib/Target/AArch64/
H A DAArch64ISelLowering.cpp2341 return DAG.getNode( in LowerVectorFP_TO_INT()
2376 return DAG.getNode( in LowerFP_TO_INT()
2433 return DAG.getNode( in LowerINT_TO_FP()
3868 if (InFlag.getNode()) in LowerCall()
3972 if (Flag.getNode()) in LowerReturn()
4029 return DAG.getNode( in getAddrLarge()
4637 Val = DAG.getNode( in LowerCTPOP()
6704 return DAG.getNode( in LowerVECTOR_SHUFFLE()
7853 if (!Cmp.getNode()) in LowerVSETCC()
7897 return DAG.getNode( in LowerVECREDUCE()
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/freebsd-12.1/contrib/llvm/lib/Target/SystemZ/
H A DSystemZSelectionDAGInfo.cpp42 return DAG.getNode(Loop, DL, MVT::Other, Chain, Dst, Src, in emitMemMem()
45 return DAG.getNode(Sequence, DL, MVT::Other, Chain, Dst, Src, in emitMemMem()
104 Dst = DAG.getNode(ISD::ADD, DL, PtrVT, Dst, in EmitTargetCodeForMemset()
117 SDValue Dst2 = DAG.getNode(ISD::ADD, DL, PtrVT, Dst, in EmitTargetCodeForMemset()
136 SDValue DstPlus1 = DAG.getNode(ISD::ADD, DL, PtrVT, Dst, in EmitTargetCodeForMemset()
173 SDValue SHL = DAG.getNode(ISD::SHL, DL, MVT::i32, IPM, in addIPMSequence()
175 SDValue SRA = DAG.getNode(ISD::SRA, DL, MVT::i32, SHL, in addIPMSequence()
203 Char = DAG.getNode(ISD::AND, DL, MVT::i32, Char, in EmitTargetCodeForMemchr()
205 SDValue Limit = DAG.getNode(ISD::ADD, DL, PtrVT, Src, Length); in EmitTargetCodeForMemchr()
217 End = DAG.getNode(SystemZISD::SELECT_CCMASK, DL, PtrVT, Ops); in EmitTargetCodeForMemchr()
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H A DSystemZISelLowering.cpp1396 if (Glue.getNode()) in LowerCall()
1500 if (Glue.getNode()) in LowerReturn()
1696 return Intr.getNode(); in emitIntrinsicWithCCAndChain()
1710 return Intr.getNode(); in emitIntrinsicWithCC()
2322 if (!C.Op1.getNode()) { in emitCmp()
3222 SDNode *N = Op.getNode(); in lowerXALUO()
3529 if (NegSrc2.getNode()) in lowerATOMIC_LOAD_SUB()
4084 while (Op.getNode()) { in add()
4379 if (!Op.getNode()) { in tryBuildVectorShuffle()
4573 if (Op.getNode()) in lowerBUILD_VECTOR()
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H A DSystemZISelDAGToDAG.cpp78 if (Base.getNode()) in dump()
79 Base.getNode()->dump(DAG); in dump()
85 if (Index.getNode()) in dump()
86 Index.getNode()->dump(DAG); in dump()
581 !shouldUseLA(AM.Base.getNode(), AM.Disp, AM.Index.getNode())) in selectAddress()
619 if (!Base.getNode()) in getAddressOperands()
647 if (!Index.getNode()) in getAddressOperands()
692 Regs[0].getNode() && Regs[1].getNode()) { in selectBDVAddr12Only()
1002 N = New.getNode(); in tryRISBGZero()
1106 if (Op0.getNode()) in splitLargeImmediate()
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/freebsd-12.1/contrib/llvm/lib/Target/Mips/
H A DMipsSEISelLowering.cpp656 if (!IfClr.getNode()) { in performORCombine()
693 if (!IfClr.getNode()) in performORCombine()
696 assert(Cond.getNode() && IfSet.getNode()); in performORCombine()
796 return DAG.getNode(ISD::SHL, DL, VT, X, in genConstMult()
1047 if (Val.getNode()) { in PerformDAGCombine()
1300 if (In64.getNode()) in lowerDSPIntr()
1444 Exp2Imm = DAG.getNode( in lowerMSABinaryBitImmIntr()
1451 if (!Exp2Imm.getNode()) { in lowerMSABinaryBitImmIntr()
1579 return DAG.getNode(ISD::VSELECT, DL, VecTy, in lowerINTRINSIC_WO_CHAIN()
1854 return DAG.getNode( in lowerINTRINSIC_WO_CHAIN()
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/freebsd-12.1/contrib/llvm/lib/Target/Lanai/
H A DLanaiISelLowering.cpp354 if (Result.getNode()) { in LowerAsmOperandForConstraint()
586 if (Flag.getNode()) in LowerReturn()
590 return DAG.getNode(Opc, DL, MVT::Other, in LowerReturn()
690 if (StackPtr.getNode() == nullptr) in LowerCCCCallTo()
751 if (InFlag.getNode()) in LowerCCCCallTo()
946 Res = DAG.getNode(ISD::SHL, DL, VT, V, in LowerMUL()
1140 return DAG.getNode(ISD::OR, DL, MVT::i32, in LowerConstantPool()
1305 SDValue NegatedPlus32 = DAG.getNode( in LowerSRL_PARTS()
1447 if (N0.getNode()->hasOneUse()) in combineSelectAndUseCommutative()
1450 if (N1.getNode()->hasOneUse()) in combineSelectAndUseCommutative()
[all …]
/freebsd-12.1/contrib/llvm/lib/Target/X86/
H A DX86ISelLowering.cpp2619 if (Flag.getNode()) in LowerReturn()
7080 if (!V1.getNode()) in LowerBuildVectorv4x32()
8931 assert(!VarElt.getNode() && !InsIndex.getNode() && in LowerBUILD_VECTOR()
9049 if (Op.getNode()->isOnlyUserOf(Item.getNode())) in LowerBUILD_VECTOR()
19169 if (!Src.getNode()) in LowerAndToBT()
20002 if (Op1Scalar.getNode() && Op2Scalar.getNode()) { in LowerSELECT()
25028 M = DAG.getNode( in LowerRotate()
25038 M = DAG.getNode( in LowerRotate()
25048 M = DAG.getNode( in LowerRotate()
26310 if (!Res.getNode()) in LowerOperationWrapper()
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H A DX86ISelDAGToDAG.cpp90 IndexReg.getNode() != nullptr || Base_Reg.getNode() != nullptr; in hasBaseOrIndexReg()
111 if (Base_Reg.getNode()) in dump()
119 if (IndexReg.getNode()) in dump()
290 if (AM.Segment.getNode()) in getAddressOperands()
654 if (Chain.getNode() == Load.getNode()) in moveBelowOrigChain()
660 if (Chain.getOperand(i).getNode() == Load.getNode()) in moveBelowOrigChain()
690 if (Callee.getNode() == Chain.getNode() || !Callee.hasOneUse()) in isCalleeLoad()
713 if (Chain.getOperand(0).getNode() == Callee.getNode()) in isCalleeLoad()
1756 (AM.Segment.getNode() && !Backup.Segment.getNode()) >= 2) in matchAddressRecursively()
2147 if (AM.IndexReg.getNode()) in selectLEAAddr()
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/freebsd-12.1/contrib/llvm/lib/Target/Sparc/
H A DSparcISelLowering.cpp284 if (Flag.getNode()) in LowerReturn_32()
363 if (Flag.getNode()) in LowerReturn_64()
970 if (InFlag.getNode()) in LowerCall_32()
1272 if (InGlue.getNode()) in LowerCall_64()
1314 if (!RV.getNode()) { in LowerCall_64()
1985 L44 = DAG.getNode(SPISD::Lo, DL, VT, L44); in makeAddress()
2116 return DAG.getNode(ISD::ADD, DL, PtrVT, in LowerGlobalTLSAddress()
2521 SDNode *Node = Op.getNode(); in LowerVAARG()
2609 SDValue Chain = DAG.getNode(SPISD::FLUSHW, in getFLUSHW()
2682 SDValue Ptr = DAG.getNode(ISD::ADD, in LowerRETURNADDR()
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/freebsd-12.1/contrib/llvm/lib/Target/PowerPC/
H A DPPCISelLowering.cpp1397 else if (ISD::isEXTLoad(Op.getNode()) || ISD::isNON_EXTLoad(Op.getNode())) { in isFloatingPointZero()
2114 if (!OpVal.getNode()) in get_VSPLTI_elt()
2493 if (Val == Base || Base.getNode()->isPredecessorOf(Val.getNode())) in getPreIndexedAddressParts()
4724 .getNode(); in isBLACompatibleAddress()
5084 if (Callee.getNode()) { in PrepareCall()
5192 if (InFlag.getNode()) in FinishCall()
6694 if (Flag.getNode()) in LowerReturn()
7013 Tmp = DAG.getNode( in LowerFP_TO_INTForReuse()
7077 Tmp = DAG.getNode( in LowerFP_TO_INTDirectMove()
7217 assert(TF.getNode() != NewResChain.getNode() && in spliceIntoChain()
[all …]

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