Lines Matching refs:getNode
932 New = TLO.DAG.getNode(Op.getOpcode(), DL, VT, Op.getOperand(0), in optimizeLogicalImm()
1508 LHS = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f32, LHS); in emitComparison()
1509 RHS = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f32, RHS); in emitComparison()
1512 return DAG.getNode(AArch64ISD::FCMP, dl, VT, LHS, RHS); in emitComparison()
1540 return DAG.getNode(Opcode, dl, DAG.getVTList(VT, MVT_CC), LHS, RHS) in emitComparison()
1609 LHS = DAG.getNode(ISD::FP_EXTEND, DL, MVT::f32, LHS); in emitConditionalComparison()
1610 RHS = DAG.getNode(ISD::FP_EXTEND, DL, MVT::f32, RHS); in emitConditionalComparison()
1628 return DAG.getNode(Opcode, DL, MVT_CC, LHS, RHS, NZCVOp, Condition, CCOp); in emitConditionalComparison()
1731 if (!CCOp.getNode()) in emitConjunctionRec()
1870 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(RHS.getNode())) { in getAArch64Cmp()
1969 LHS.getNode()->hasNUsesOfValue(1, 0)) { in getAArch64Cmp()
1973 DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, LHS.getValueType(), LHS, in getAArch64Cmp()
2037 LHS = DAG.getNode(ExtendOpc, DL, MVT::i64, LHS); in getAArch64XALUOOp()
2038 RHS = DAG.getNode(ExtendOpc, DL, MVT::i64, RHS); in getAArch64XALUOOp()
2039 SDValue Mul = DAG.getNode(ISD::MUL, DL, MVT::i64, LHS, RHS); in getAArch64XALUOOp()
2040 SDValue Add = DAG.getNode(ISD::ADD, DL, MVT::i64, Mul, in getAArch64XALUOOp()
2046 Value = DAG.getNode(ISD::TRUNCATE, DL, MVT::i32, Add); in getAArch64XALUOOp()
2053 SDValue UpperBits = DAG.getNode(ISD::SRL, DL, MVT::i64, Add, in getAArch64XALUOOp()
2055 UpperBits = DAG.getNode(ISD::TRUNCATE, DL, MVT::i32, UpperBits); in getAArch64XALUOOp()
2056 SDValue LowerBits = DAG.getNode(ISD::SRA, DL, MVT::i32, Value, in getAArch64XALUOOp()
2061 Overflow = DAG.getNode(AArch64ISD::SUBS, DL, VTs, UpperBits, LowerBits) in getAArch64XALUOOp()
2069 SDValue UpperBits = DAG.getNode(ISD::SRL, DL, MVT::i64, Mul, in getAArch64XALUOOp()
2073 DAG.getNode(AArch64ISD::SUBS, DL, VTs, in getAArch64XALUOOp()
2081 Value = DAG.getNode(ISD::MUL, DL, MVT::i64, LHS, RHS); in getAArch64XALUOOp()
2083 SDValue UpperBits = DAG.getNode(ISD::MULHS, DL, MVT::i64, LHS, RHS); in getAArch64XALUOOp()
2084 SDValue LowerBits = DAG.getNode(ISD::SRA, DL, MVT::i64, Value, in getAArch64XALUOOp()
2089 Overflow = DAG.getNode(AArch64ISD::SUBS, DL, VTs, UpperBits, LowerBits) in getAArch64XALUOOp()
2092 SDValue UpperBits = DAG.getNode(ISD::MULHU, DL, MVT::i64, LHS, RHS); in getAArch64XALUOOp()
2095 DAG.getNode(AArch64ISD::SUBS, DL, VTs, in getAArch64XALUOOp()
2107 Value = DAG.getNode(Opc, DL, VTs, LHS, RHS); in getAArch64XALUOOp()
2151 return DAG.getNode(AArch64ISD::CSEL, dl, Op.getValueType(), TVal, FVal, in LowerXOR()
2198 TVal = DAG.getNode(ISD::XOR, dl, Other.getValueType(), Other, in LowerXOR()
2201 return DAG.getNode(AArch64ISD::CSEL, dl, Sel.getValueType(), FVal, TVal, in LowerXOR()
2239 return DAG.getNode(Opc, SDLoc(Op), VTs, Op.getOperand(0), Op.getOperand(1)); in LowerADDC_ADDE_SUBC_SUBE()
2240 return DAG.getNode(Opc, SDLoc(Op), VTs, Op.getOperand(0), Op.getOperand(1), in LowerADDC_ADDE_SUBC_SUBE()
2263 Overflow = DAG.getNode(AArch64ISD::CSEL, dl, MVT::i32, FVal, TVal, in LowerXALUO()
2267 return DAG.getNode(ISD::MERGE_VALUES, dl, VTs, Value, Overflow); in LowerXALUO()
2297 return DAG.getNode(AArch64ISD::PREFETCH, DL, MVT::Other, Op.getOperand(0), in LowerPREFETCH()
2341 return DAG.getNode( in LowerVectorFP_TO_INT()
2343 DAG.getNode(ISD::FP_EXTEND, dl, NewVT, Op.getOperand(0))); in LowerVectorFP_TO_INT()
2349 DAG.getNode(Op.getOpcode(), dl, InVT.changeVectorElementTypeToInteger(), in LowerVectorFP_TO_INT()
2351 return DAG.getNode(ISD::TRUNCATE, dl, VT, Cv); in LowerVectorFP_TO_INT()
2359 SDValue Ext = DAG.getNode(ISD::FP_EXTEND, dl, ExtVT, Op.getOperand(0)); in LowerVectorFP_TO_INT()
2360 return DAG.getNode(Op.getOpcode(), dl, VT, Ext); in LowerVectorFP_TO_INT()
2376 return DAG.getNode( in LowerFP_TO_INT()
2378 DAG.getNode(ISD::FP_EXTEND, dl, MVT::f32, Op.getOperand(0))); in LowerFP_TO_INT()
2409 In = DAG.getNode(Op.getOpcode(), dl, CastVT, In); in LowerVectorINT_TO_FP()
2410 return DAG.getNode(ISD::FP_ROUND, dl, VT, In, DAG.getIntPtrConstant(0, dl)); in LowerVectorINT_TO_FP()
2417 In = DAG.getNode(CastOpc, dl, CastVT, In); in LowerVectorINT_TO_FP()
2418 return DAG.getNode(Op.getOpcode(), dl, VT, In); in LowerVectorINT_TO_FP()
2433 return DAG.getNode( in LowerINT_TO_FP()
2435 DAG.getNode(Op.getOpcode(), dl, MVT::f32, Op.getOperand(0)), in LowerINT_TO_FP()
2498 Op = DAG.getNode(ISD::ANY_EXTEND, DL, MVT::i32, Op.getOperand(0)); in LowerBITCAST()
2499 Op = DAG.getNode(ISD::BITCAST, DL, MVT::f32, Op); in LowerBITCAST()
2537 return DAG.getNode(ExtOpcode, SDLoc(N), NewVT, N); in addRequiredExtensionForVectorMULL()
2603 SDNode *N0 = N->getOperand(0).getNode(); in isAddSubSExt()
2604 SDNode *N1 = N->getOperand(1).getNode(); in isAddSubSExt()
2614 SDNode *N0 = N->getOperand(0).getNode(); in isAddSubZExt()
2615 SDNode *N1 = N->getOperand(1).getNode(); in isAddSubZExt()
2630 SDValue FPCR_64 = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, MVT::i64, in LowerFLT_ROUNDS_()
2633 SDValue FPCR_32 = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, FPCR_64); in LowerFLT_ROUNDS_()
2634 SDValue FltRounds = DAG.getNode(ISD::ADD, dl, MVT::i32, FPCR_32, in LowerFLT_ROUNDS_()
2636 SDValue RMODE = DAG.getNode(ISD::SRL, dl, MVT::i32, FltRounds, in LowerFLT_ROUNDS_()
2638 return DAG.getNode(ISD::AND, dl, MVT::i32, RMODE, in LowerFLT_ROUNDS_()
2648 SDNode *N0 = Op.getOperand(0).getNode(); in LowerMUL()
2649 SDNode *N1 = Op.getOperand(1).getNode(); in LowerMUL()
2696 return DAG.getNode(NewOpc, DL, VT, Op0, Op1); in LowerMUL()
2701 SDValue N00 = skipExtensionForVectorMULL(N0->getOperand(0).getNode(), DAG); in LowerMUL()
2702 SDValue N01 = skipExtensionForVectorMULL(N0->getOperand(1).getNode(), DAG); in LowerMUL()
2704 return DAG.getNode(N0->getOpcode(), DL, VT, in LowerMUL()
2705 DAG.getNode(NewOpc, DL, VT, in LowerMUL()
2706 DAG.getNode(ISD::BITCAST, DL, Op1VT, N00), Op1), in LowerMUL()
2707 DAG.getNode(NewOpc, DL, VT, in LowerMUL()
2708 DAG.getNode(ISD::BITCAST, DL, Op1VT, N01), Op1)); in LowerMUL()
2719 return DAG.getNode(AArch64ISD::THREAD_POINTER, dl, PtrVT); in LowerINTRINSIC_WO_CHAIN()
2724 SDValue Result = DAG.getNode(ISD::BITCAST, dl, MVT::v1i64, in LowerINTRINSIC_WO_CHAIN()
2726 Result = DAG.getNode(ISD::ABS, dl, MVT::v1i64, Result); in LowerINTRINSIC_WO_CHAIN()
2727 return DAG.getNode(ISD::BITCAST, dl, MVT::i64, Result); in LowerINTRINSIC_WO_CHAIN()
2729 return DAG.getNode(ISD::ABS, dl, Ty, Op.getOperand(1)); in LowerINTRINSIC_WO_CHAIN()
2735 return DAG.getNode(ISD::SMAX, dl, Op.getValueType(), in LowerINTRINSIC_WO_CHAIN()
2738 return DAG.getNode(ISD::UMAX, dl, Op.getValueType(), in LowerINTRINSIC_WO_CHAIN()
2741 return DAG.getNode(ISD::SMIN, dl, Op.getValueType(), in LowerINTRINSIC_WO_CHAIN()
2744 return DAG.getNode(ISD::UMIN, dl, Op.getValueType(), in LowerINTRINSIC_WO_CHAIN()
2797 SDValue TruncExt = DAG.getNode(ISD::CONCAT_VECTORS, DL, MVT::v8i16, in LowerTruncateVectorStore()
2799 SDValue Trunc = DAG.getNode(ISD::TRUNCATE, DL, MVT::v8i8, TruncExt); in LowerTruncateVectorStore()
2801 Trunc = DAG.getNode(ISD::BITCAST, DL, MVT::v2i32, Trunc); in LowerTruncateVectorStore()
2802 SDValue ExtractTrunc = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::i32, in LowerTruncateVectorStore()
3112 ArgValue = DAG.getNode(ISD::BITCAST, DL, VA.getValVT(), ArgValue); in LowerFormalArguments()
3270 DAG.getNode(ISD::ADD, DL, PtrVT, FIN, DAG.getConstant(8, DL, PtrVT)); in saveVarArgRegisters()
3298 FIN = DAG.getNode(ISD::ADD, DL, PtrVT, FIN, in saveVarArgRegisters()
3307 Chain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other, MemOps); in saveVarArgRegisters()
3351 Val = DAG.getNode(ISD::BITCAST, DL, VA.getValVT(), Val); in LowerCallResult()
3499 for (SDNode::use_iterator U = DAG.getEntryNode().getNode()->use_begin(), in addTokenForArgument()
3500 UE = DAG.getEntryNode().getNode()->use_end(); in addTokenForArgument()
3515 return DAG.getNode(ISD::TokenFactor, SDLoc(Chain), MVT::Other, ArgChains); in addTokenForArgument()
3681 Arg = DAG.getNode(ISD::SIGN_EXTEND, DL, VA.getLocVT(), Arg); in LowerCall()
3684 Arg = DAG.getNode(ISD::ZERO_EXTEND, DL, VA.getLocVT(), Arg); in LowerCall()
3689 Arg = DAG.getNode(ISD::TRUNCATE, DL, MVT::i1, Arg); in LowerCall()
3690 Arg = DAG.getNode(ISD::ZERO_EXTEND, DL, MVT::i8, Arg); in LowerCall()
3692 Arg = DAG.getNode(ISD::ANY_EXTEND, DL, VA.getLocVT(), Arg); in LowerCall()
3695 Arg = DAG.getNode(ISD::BITCAST, DL, VA.getLocVT(), Arg); in LowerCall()
3698 Arg = DAG.getNode(ISD::FP_EXTEND, DL, VA.getLocVT(), Arg); in LowerCall()
3732 PtrOff = DAG.getNode(ISD::ADD, DL, PtrVT, StackPtr, PtrOff); in LowerCall()
3749 DstAddr = DAG.getNode(ISD::ADD, DL, PtrVT, StackPtr, PtrOff); in LowerCall()
3770 Arg = DAG.getNode(ISD::TRUNCATE, DL, VA.getValVT(), Arg); in LowerCall()
3779 Chain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other, MemOpChains); in LowerCall()
3798 Callee = DAG.getNode(AArch64ISD::LOADgot, DL, PtrVT, Callee); in LowerCall()
3812 Callee = DAG.getNode(AArch64ISD::LOADgot, DL, PtrVT, Callee); in LowerCall()
3868 if (InFlag.getNode()) in LowerCall()
3877 return DAG.getNode(AArch64ISD::TC_RETURN, DL, NodeTys, Ops); in LowerCall()
3881 Chain = DAG.getNode(AArch64ISD::CALL, DL, NodeTys, Ops); in LowerCall()
3942 Arg = DAG.getNode(ISD::TRUNCATE, DL, MVT::i1, Arg); in LowerReturn()
3943 Arg = DAG.getNode(ISD::ZERO_EXTEND, DL, VA.getLocVT(), Arg); in LowerReturn()
3947 Arg = DAG.getNode(ISD::BITCAST, DL, VA.getLocVT(), Arg); in LowerReturn()
3972 if (Flag.getNode()) in LowerReturn()
3975 return DAG.getNode(AArch64ISD::RET_FLAG, DL, MVT::Other, RetOps); in LowerReturn()
4018 return DAG.getNode(AArch64ISD::LOADgot, DL, Ty, GotAddr); in getGOT()
4029 return DAG.getNode( in getAddrLarge()
4047 SDValue ADRP = DAG.getNode(AArch64ISD::ADRP, DL, Ty, Hi); in getAddr()
4048 return DAG.getNode(AArch64ISD::ADDlow, DL, Ty, ADRP, Lo); in getAddr()
4059 return DAG.getNode(AArch64ISD::ADR, DL, Ty, Sym); in getAddrTiny()
4135 SDValue DescAddr = DAG.getNode(AArch64ISD::LOADgot, DL, PtrVT, TLVPAddr); in LowerDarwinGlobalTLSAddress()
4164 DAG.getNode(AArch64ISD::CALL, DL, DAG.getVTList(MVT::Other, MVT::Glue), in LowerDarwinGlobalTLSAddress()
4197 DAG.getNode(AArch64ISD::TLSDESC_CALLSEQ, DL, NodeTys, {Chain, SymAddr}); in LowerELFTLSDescCallSeq()
4230 SDValue ThreadBase = DAG.getNode(AArch64ISD::THREAD_POINTER, DL, PtrVT); in LowerELFGlobalTLSAddress()
4252 TPOff = DAG.getNode(AArch64ISD::LOADgot, DL, PtrVT, TPOff); in LowerELFGlobalTLSAddress()
4300 return DAG.getNode(ISD::ADD, DL, PtrVT, ThreadBase, TPOff); in LowerELFGlobalTLSAddress()
4317 DAG.getNode(ISD::ADD, DL, PtrVT, TEB, DAG.getIntPtrConstant(0x58, DL)); in LowerWindowsGlobalTLSAddress()
4329 SDValue ADRP = DAG.getNode(AArch64ISD::ADRP, DL, PtrVT, TLSIndexHi); in LowerWindowsGlobalTLSAddress()
4331 DAG.getNode(AArch64ISD::ADDlow, DL, PtrVT, ADRP, TLSIndexLo); in LowerWindowsGlobalTLSAddress()
4337 TLSIndex = DAG.getNode(ISD::ZERO_EXTEND, DL, PtrVT, TLSIndex); in LowerWindowsGlobalTLSAddress()
4338 SDValue Slot = DAG.getNode(ISD::SHL, DL, PtrVT, TLSIndex, in LowerWindowsGlobalTLSAddress()
4341 DAG.getNode(ISD::ADD, DL, PtrVT, TLSArray, Slot), in LowerWindowsGlobalTLSAddress()
4358 Addr = DAG.getNode(AArch64ISD::ADDlow, DL, PtrVT, Addr, TGALo); in LowerWindowsGlobalTLSAddress()
4401 if (!RHS.getNode()) { in LowerBR_CC()
4424 return DAG.getNode(AArch64ISD::BRCOND, dl, MVT::Other, Chain, Dest, CCVal, in LowerBR_CC()
4446 return DAG.getNode(AArch64ISD::TBZ, dl, MVT::Other, Chain, Test, in LowerBR_CC()
4451 return DAG.getNode(AArch64ISD::CBZ, dl, MVT::Other, Chain, LHS, Dest); in LowerBR_CC()
4462 return DAG.getNode(AArch64ISD::TBNZ, dl, MVT::Other, Chain, Test, in LowerBR_CC()
4467 return DAG.getNode(AArch64ISD::CBNZ, dl, MVT::Other, Chain, LHS, Dest); in LowerBR_CC()
4473 return DAG.getNode(AArch64ISD::TBNZ, dl, MVT::Other, Chain, LHS, in LowerBR_CC()
4483 return DAG.getNode(AArch64ISD::TBZ, dl, MVT::Other, Chain, LHS, in LowerBR_CC()
4489 return DAG.getNode(AArch64ISD::BRCOND, dl, MVT::Other, Chain, Dest, CCVal, in LowerBR_CC()
4503 DAG.getNode(AArch64ISD::BRCOND, dl, MVT::Other, Chain, Dest, CC1Val, Cmp); in LowerBR_CC()
4506 return DAG.getNode(AArch64ISD::BRCOND, dl, MVT::Other, BR1, Dest, CC2Val, in LowerBR_CC()
4523 In2 = DAG.getNode(ISD::FP_EXTEND, DL, VT, In2); in LowerFCOPYSIGN()
4525 In2 = DAG.getNode(ISD::FP_ROUND, DL, VT, In2, DAG.getIntPtrConstant(0, DL)); in LowerFCOPYSIGN()
4538 VecVal1 = DAG.getNode(ISD::BITCAST, DL, VecVT, In1); in LowerFCOPYSIGN()
4539 VecVal2 = DAG.getNode(ISD::BITCAST, DL, VecVT, In2); in LowerFCOPYSIGN()
4569 BuildVec = DAG.getNode(ISD::BITCAST, DL, MVT::v2f64, BuildVec); in LowerFCOPYSIGN()
4570 BuildVec = DAG.getNode(ISD::FNEG, DL, MVT::v2f64, BuildVec); in LowerFCOPYSIGN()
4571 BuildVec = DAG.getNode(ISD::BITCAST, DL, MVT::v2i64, BuildVec); in LowerFCOPYSIGN()
4575 DAG.getNode(AArch64ISD::BIT, DL, VecVT, VecVal1, VecVal2, BuildVec); in LowerFCOPYSIGN()
4584 return DAG.getNode(ISD::BITCAST, DL, VT, Sel); in LowerFCOPYSIGN()
4609 Val = DAG.getNode(ISD::ZERO_EXTEND, DL, MVT::i64, Val); in LowerCTPOP()
4610 Val = DAG.getNode(ISD::BITCAST, DL, MVT::v8i8, Val); in LowerCTPOP()
4612 SDValue CtPop = DAG.getNode(ISD::CTPOP, DL, MVT::v8i8, Val); in LowerCTPOP()
4613 SDValue UaddLV = DAG.getNode( in LowerCTPOP()
4618 UaddLV = DAG.getNode(ISD::ZERO_EXTEND, DL, MVT::i64, UaddLV); in LowerCTPOP()
4628 Val = DAG.getNode(ISD::CTPOP, DL, VT8Bit, Val); in LowerCTPOP()
4637 Val = DAG.getNode( in LowerCTPOP()
4666 if (!RHS.getNode()) { in LowerSETCC()
4681 return DAG.getNode(AArch64ISD::CSEL, dl, VT, FVal, TVal, CCVal, Cmp); in LowerSETCC()
4701 return DAG.getNode(AArch64ISD::CSEL, dl, VT, FVal, TVal, CC1Val, Cmp); in LowerSETCC()
4711 DAG.getNode(AArch64ISD::CSEL, dl, VT, TVal, FVal, CC1Val, Cmp); in LowerSETCC()
4714 return DAG.getNode(AArch64ISD::CSEL, dl, VT, TVal, CS1, CC2Val, Cmp); in LowerSETCC()
4729 if (!RHS.getNode()) { in LowerSELECT_CC()
4737 LHS = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f32, LHS); in LowerSELECT_CC()
4738 RHS = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f32, RHS); in LowerSELECT_CC()
4858 return DAG.getNode(Opcode, dl, VT, TVal, FVal, CCVal, Cmp); in LowerSELECT_CC()
4893 SDValue CS1 = DAG.getNode(AArch64ISD::CSEL, dl, VT, TVal, FVal, CC1Val, Cmp); in LowerSELECT_CC()
4899 return DAG.getNode(AArch64ISD::CSEL, dl, VT, TVal, CS1, CC2Val, Cmp); in LowerSELECT_CC()
4936 return DAG.getNode(AArch64ISD::CSEL, DL, Op.getValueType(), TVal, FVal, in LowerSELECT()
4977 int JTI = cast<JumpTableSDNode>(JT.getNode())->getIndex(); in LowerBR_JT()
4982 return DAG.getNode(ISD::BRIND, DL, MVT::Other, Op.getOperand(0), in LowerBR_JT()
5068 DAG.getNode(ISD::ADD, DL, PtrVT, VAList, DAG.getConstant(8, DL, PtrVT)); in LowerAAPCS_VASTART()
5071 GRTop = DAG.getNode(ISD::ADD, DL, PtrVT, GRTop, in LowerAAPCS_VASTART()
5083 VRTopAddr = DAG.getNode(ISD::ADD, DL, PtrVT, VAList, in LowerAAPCS_VASTART()
5087 VRTop = DAG.getNode(ISD::ADD, DL, PtrVT, VRTop, in LowerAAPCS_VASTART()
5097 DAG.getNode(ISD::ADD, DL, PtrVT, VAList, DAG.getConstant(24, DL, PtrVT)); in LowerAAPCS_VASTART()
5104 DAG.getNode(ISD::ADD, DL, PtrVT, VAList, DAG.getConstant(28, DL, PtrVT)); in LowerAAPCS_VASTART()
5109 return DAG.getNode(ISD::TokenFactor, DL, MVT::Other, MemOps); in LowerAAPCS_VASTART()
5158 VAList = DAG.getNode(ISD::ADD, DL, PtrVT, VAList, in LowerVAARG()
5160 VAList = DAG.getNode(ISD::AND, DL, PtrVT, VAList, in LowerVAARG()
5180 SDValue VANext = DAG.getNode(ISD::ADD, DL, PtrVT, VAList, in LowerVAARG()
5192 SDValue NarrowFP = DAG.getNode(ISD::FP_ROUND, DL, VT, WideFP.getValue(0), in LowerVAARG()
5289 return DAG.getNode(ISD::ADD, DL, VT, FrameAddr, Offset); in LowerADDROFRETURNADDR()
5305 DAG.getNode(ISD::ADD, DL, VT, FrameAddr, Offset), in LowerRETURNADDR()
5329 SDValue RevShAmt = DAG.getNode(ISD::SUB, dl, MVT::i64, in LowerShiftRightParts()
5331 SDValue HiBitsForLo = DAG.getNode(ISD::SHL, dl, VT, ShOpHi, RevShAmt); in LowerShiftRightParts()
5339 DAG.getNode(AArch64ISD::CSEL, dl, VT, DAG.getConstant(0, dl, MVT::i64), in LowerShiftRightParts()
5342 SDValue ExtraShAmt = DAG.getNode(ISD::SUB, dl, MVT::i64, ShAmt, in LowerShiftRightParts()
5345 SDValue LoBitsForLo = DAG.getNode(ISD::SRL, dl, VT, ShOpLo, ShAmt); in LowerShiftRightParts()
5347 DAG.getNode(ISD::OR, dl, VT, LoBitsForLo, HiBitsForLo); in LowerShiftRightParts()
5352 SDValue LoForBigShift = DAG.getNode(Opc, dl, VT, ShOpHi, ExtraShAmt); in LowerShiftRightParts()
5353 SDValue Lo = DAG.getNode(AArch64ISD::CSEL, dl, VT, LoForBigShift, in LowerShiftRightParts()
5358 SDValue HiForNormalShift = DAG.getNode(Opc, dl, VT, ShOpHi, ShAmt); in LowerShiftRightParts()
5361 ? DAG.getNode(Opc, dl, VT, ShOpHi, in LowerShiftRightParts()
5364 SDValue Hi = DAG.getNode(AArch64ISD::CSEL, dl, VT, HiForBigShift, in LowerShiftRightParts()
5384 SDValue RevShAmt = DAG.getNode(ISD::SUB, dl, MVT::i64, in LowerShiftLeftParts()
5386 SDValue LoBitsForHi = DAG.getNode(ISD::SRL, dl, VT, ShOpLo, RevShAmt); in LowerShiftLeftParts()
5394 DAG.getNode(AArch64ISD::CSEL, dl, VT, DAG.getConstant(0, dl, MVT::i64), in LowerShiftLeftParts()
5397 SDValue ExtraShAmt = DAG.getNode(ISD::SUB, dl, MVT::i64, ShAmt, in LowerShiftLeftParts()
5399 SDValue HiBitsForHi = DAG.getNode(ISD::SHL, dl, VT, ShOpHi, ShAmt); in LowerShiftLeftParts()
5401 DAG.getNode(ISD::OR, dl, VT, LoBitsForHi, HiBitsForHi); in LowerShiftLeftParts()
5403 SDValue HiForBigShift = DAG.getNode(ISD::SHL, dl, VT, ShOpLo, ExtraShAmt); in LowerShiftLeftParts()
5408 SDValue Hi = DAG.getNode(AArch64ISD::CSEL, dl, VT, HiForBigShift, in LowerShiftLeftParts()
5414 SDValue LoForNormalShift = DAG.getNode(ISD::SHL, dl, VT, ShOpLo, ShAmt); in LowerShiftLeftParts()
5415 SDValue Lo = DAG.getNode(AArch64ISD::CSEL, dl, VT, LoForBigShift, in LowerShiftLeftParts()
5480 return DAG.getNode(Opcode, SDLoc(Operand), VT, Operand); in getEstimate()
5504 SDValue Step = DAG.getNode(ISD::FMUL, DL, VT, Estimate, Estimate, in getSqrtEstimate()
5506 Step = DAG.getNode(AArch64ISD::FRSQRTS, DL, VT, Operand, Step, Flags); in getSqrtEstimate()
5507 Estimate = DAG.getNode(ISD::FMUL, DL, VT, Estimate, Step, Flags); in getSqrtEstimate()
5515 Estimate = DAG.getNode(ISD::FMUL, DL, VT, Operand, Estimate, Flags); in getSqrtEstimate()
5517 Estimate = DAG.getNode(VT.isVector() ? ISD::VSELECT : ISD::SELECT, DL, in getSqrtEstimate()
5543 SDValue Step = DAG.getNode(AArch64ISD::FRECPS, DL, VT, Operand, in getRecipEstimate()
5545 Estimate = DAG.getNode(ISD::FMUL, DL, VT, Estimate, Step, Flags); in getRecipEstimate()
5873 if (Result.getNode()) { in LowerAsmOperandForConstraint()
5894 return DAG.getNode(ISD::INSERT_SUBVECTOR, DL, WideTy, DAG.getUNDEF(WideTy), in WidenVector()
6019 DAG.getNode(ISD::CONCAT_VECTORS, dl, DestVT, Src.ShuffleVec, in ReconstructShuffle()
6035 DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, DestVT, Src.ShuffleVec, in ReconstructShuffle()
6041 DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, DestVT, Src.ShuffleVec, in ReconstructShuffle()
6046 DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, DestVT, Src.ShuffleVec, in ReconstructShuffle()
6049 DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, DestVT, Src.ShuffleVec, in ReconstructShuffle()
6053 Src.ShuffleVec = DAG.getNode(AArch64ISD::EXT, dl, DestVT, VEXTSrc1, in ReconstructShuffle()
6068 Src.ShuffleVec = DAG.getNode(ISD::BITCAST, dl, ShuffleVT, Src.ShuffleVec); in ReconstructShuffle()
6119 SDValue V = DAG.getNode(ISD::BITCAST, dl, VT, Shuffle); in ReconstructShuffle()
6394 V0 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, CastVT, V0, in tryFormConcatFromShuffle()
6398 V1 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, CastVT, V1, in tryFormConcatFromShuffle()
6401 return DAG.getNode(ISD::CONCAT_VECTORS, DL, VT, V0, V1); in tryFormConcatFromShuffle()
6450 return DAG.getNode(AArch64ISD::REV64, dl, VT, OpLHS); in GeneratePerfectShuffle()
6454 return DAG.getNode(AArch64ISD::REV32, dl, VT, OpLHS); in GeneratePerfectShuffle()
6457 return DAG.getNode(AArch64ISD::REV16, dl, VT, OpLHS); in GeneratePerfectShuffle()
6478 return DAG.getNode(Opcode, dl, VT, OpLHS, Lane); in GeneratePerfectShuffle()
6484 return DAG.getNode(AArch64ISD::EXT, dl, VT, OpLHS, OpRHS, in GeneratePerfectShuffle()
6488 return DAG.getNode(AArch64ISD::UZP1, dl, DAG.getVTList(VT, VT), OpLHS, in GeneratePerfectShuffle()
6491 return DAG.getNode(AArch64ISD::UZP2, dl, DAG.getVTList(VT, VT), OpLHS, in GeneratePerfectShuffle()
6494 return DAG.getNode(AArch64ISD::ZIP1, dl, DAG.getVTList(VT, VT), OpLHS, in GeneratePerfectShuffle()
6497 return DAG.getNode(AArch64ISD::ZIP2, dl, DAG.getVTList(VT, VT), OpLHS, in GeneratePerfectShuffle()
6500 return DAG.getNode(AArch64ISD::TRN1, dl, DAG.getVTList(VT, VT), OpLHS, in GeneratePerfectShuffle()
6503 return DAG.getNode(AArch64ISD::TRN2, dl, DAG.getVTList(VT, VT), OpLHS, in GeneratePerfectShuffle()
6533 SDValue V1Cst = DAG.getNode(ISD::BITCAST, DL, IndexVT, V1); in GenerateTBL()
6534 SDValue V2Cst = DAG.getNode(ISD::BITCAST, DL, IndexVT, V2); in GenerateTBL()
6537 if (V2.getNode()->isUndef()) { in GenerateTBL()
6539 V1Cst = DAG.getNode(ISD::CONCAT_VECTORS, DL, MVT::v16i8, V1Cst, V1Cst); in GenerateTBL()
6540 Shuffle = DAG.getNode( in GenerateTBL()
6547 V1Cst = DAG.getNode(ISD::CONCAT_VECTORS, DL, MVT::v16i8, V1Cst, V2Cst); in GenerateTBL()
6548 Shuffle = DAG.getNode( in GenerateTBL()
6560 Shuffle = DAG.getNode( in GenerateTBL()
6567 return DAG.getNode(ISD::BITCAST, DL, Op.getValueType(), Shuffle); in GenerateTBL()
6588 ShuffleVectorSDNode *SVN = cast<ShuffleVectorSDNode>(Op.getNode()); in LowerVECTOR_SHUFFLE()
6606 return DAG.getNode(AArch64ISD::DUP, dl, V1.getValueType(), in LowerVECTOR_SHUFFLE()
6612 return DAG.getNode(AArch64ISD::DUP, dl, VT, V1.getOperand(Lane)); in LowerVECTOR_SHUFFLE()
6630 return DAG.getNode(Opcode, dl, VT, V1, DAG.getConstant(Lane, dl, MVT::i64)); in LowerVECTOR_SHUFFLE()
6634 return DAG.getNode(AArch64ISD::REV64, dl, V1.getValueType(), V1, V2); in LowerVECTOR_SHUFFLE()
6636 return DAG.getNode(AArch64ISD::REV32, dl, V1.getValueType(), V1, V2); in LowerVECTOR_SHUFFLE()
6638 return DAG.getNode(AArch64ISD::REV16, dl, V1.getValueType(), V1, V2); in LowerVECTOR_SHUFFLE()
6646 return DAG.getNode(AArch64ISD::EXT, dl, V1.getValueType(), V1, V2, in LowerVECTOR_SHUFFLE()
6650 return DAG.getNode(AArch64ISD::EXT, dl, V1.getValueType(), V1, V1, in LowerVECTOR_SHUFFLE()
6657 return DAG.getNode(Opc, dl, V1.getValueType(), V1, V2); in LowerVECTOR_SHUFFLE()
6661 return DAG.getNode(Opc, dl, V1.getValueType(), V1, V2); in LowerVECTOR_SHUFFLE()
6665 return DAG.getNode(Opc, dl, V1.getValueType(), V1, V2); in LowerVECTOR_SHUFFLE()
6670 return DAG.getNode(Opc, dl, V1.getValueType(), V1, V1); in LowerVECTOR_SHUFFLE()
6674 return DAG.getNode(Opc, dl, V1.getValueType(), V1, V1); in LowerVECTOR_SHUFFLE()
6678 return DAG.getNode(Opc, dl, V1.getValueType(), V1, V1); in LowerVECTOR_SHUFFLE()
6704 return DAG.getNode( in LowerVECTOR_SHUFFLE()
6706 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, ScalarVT, SrcVec, SrcLaneV), in LowerVECTOR_SHUFFLE()
6769 SDValue Mov = DAG.getNode(NewOp, dl, MovTy, in tryAdvSIMDModImm64()
6771 return DAG.getNode(AArch64ISD::NVCAST, dl, VT, Mov); in tryAdvSIMDModImm64()
6811 Mov = DAG.getNode(NewOp, dl, MovTy, *LHS, in tryAdvSIMDModImm32()
6815 Mov = DAG.getNode(NewOp, dl, MovTy, in tryAdvSIMDModImm32()
6819 return DAG.getNode(AArch64ISD::NVCAST, dl, VT, Mov); in tryAdvSIMDModImm32()
6851 Mov = DAG.getNode(NewOp, dl, MovTy, *LHS, in tryAdvSIMDModImm16()
6855 Mov = DAG.getNode(NewOp, dl, MovTy, in tryAdvSIMDModImm16()
6859 return DAG.getNode(AArch64ISD::NVCAST, dl, VT, Mov); in tryAdvSIMDModImm16()
6887 SDValue Mov = DAG.getNode(NewOp, dl, MovTy, in tryAdvSIMDModImm321s()
6890 return DAG.getNode(AArch64ISD::NVCAST, dl, VT, Mov); in tryAdvSIMDModImm321s()
6909 SDValue Mov = DAG.getNode(NewOp, dl, MovTy, in tryAdvSIMDModImm8()
6911 return DAG.getNode(AArch64ISD::NVCAST, dl, VT, Mov); in tryAdvSIMDModImm8()
6940 SDValue Mov = DAG.getNode(NewOp, dl, MovTy, in tryAdvSIMDModImmFP()
6942 return DAG.getNode(AArch64ISD::NVCAST, dl, VT, Mov); in tryAdvSIMDModImmFP()
6955 dyn_cast<BuildVectorSDNode>(Op.getOperand(1).getNode()); in LowerVectorAND()
6959 BVN = dyn_cast<BuildVectorSDNode>(Op.getOperand(0).getNode()); in LowerVectorAND()
7075 DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT, in tryLowerToSLI()
7092 if (SDValue Res = tryLowerToSLI(Op.getNode(), DAG)) in LowerVectorOR()
7100 dyn_cast<BuildVectorSDNode>(Op.getOperand(1).getNode()); in LowerVectorOR()
7104 BVN = dyn_cast<BuildVectorSDNode>(Op.getOperand(0).getNode()); in LowerVectorOR()
7153 } else if (Lane.getNode()->isUndef()) { in NormalizeBuildVector()
7169 BuildVectorSDNode *BVN = cast<BuildVectorSDNode>(Op.getNode()); in ConstantBuildVector()
7216 BuildVectorSDNode *BVN = cast<BuildVectorSDNode>(Op.getNode()); in LowerBUILD_VECTOR()
7265 if (!ConstantValue.getNode()) in LowerBUILD_VECTOR()
7271 if (!Value.getNode()) in LowerBUILD_VECTOR()
7277 if (!Value.getNode()) { in LowerBUILD_VECTOR()
7289 return DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Value); in LowerBUILD_VECTOR()
7300 const SDNode *N = V.getNode(); in LowerBUILD_VECTOR()
7307 Vector = N0.getNode(); in LowerBUILD_VECTOR()
7313 } else if (Vector != N0.getNode()) { in LowerBUILD_VECTOR()
7338 DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, VT, SDValue(Vector, 0), in LowerBUILD_VECTOR()
7341 DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, VT, SDValue(Vector, 0), in LowerBUILD_VECTOR()
7345 return DAG.getNode(AArch64ISD::UZP1, dl, DAG.getVTList(VT, VT), LHS, in LowerBUILD_VECTOR()
7348 return DAG.getNode(AArch64ISD::UZP2, dl, DAG.getVTList(VT, VT), LHS, in LowerBUILD_VECTOR()
7361 return DAG.getNode(AArch64ISD::DUP, dl, VT, Value); in LowerBUILD_VECTOR()
7376 return DAG.getNode(Opcode, dl, VT, Value, Lane); in LowerBUILD_VECTOR()
7389 Ops.push_back(DAG.getNode(ISD::BITCAST, dl, NewType, Op.getOperand(i))); in LowerBUILD_VECTOR()
7395 if (Val.getNode()) in LowerBUILD_VECTOR()
7396 return DAG.getNode(ISD::BITCAST, dl, VT, Val); in LowerBUILD_VECTOR()
7410 Val = DAG.getNode(AArch64ISD::DUP, dl, VT, ConstantValue); in LowerBUILD_VECTOR()
7411 DAG.ReplaceAllUsesWith(Vec.getNode(), &Val); in LowerBUILD_VECTOR()
7421 Val = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, Val, V, LaneIdx); in LowerBUILD_VECTOR()
7467 Vec = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Op0); in LowerBUILD_VECTOR()
7477 Vec = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, Vec, V, LaneIdx); in LowerBUILD_VECTOR()
7515 SDValue Node = DAG.getNode(ISD::INSERT_VECTOR_ELT, DL, WideTy, WideVec, in LowerINSERT_VECTOR_ELT()
7554 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, ExtrTy, WideVec, in LowerEXTRACT_VECTOR_ELT()
7630 BuildVectorSDNode *BVN = dyn_cast<BuildVectorSDNode>(Op.getNode()); in getVShiftImm()
7681 return DAG.getNode(AArch64ISD::VSHL, DL, VT, Op.getOperand(0), in LowerVectorSRA_SRL_SHL()
7683 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT, in LowerVectorSRA_SRL_SHL()
7693 return DAG.getNode(Opc, DL, VT, Op.getOperand(0), in LowerVectorSRA_SRL_SHL()
7703 SDValue NegShift = DAG.getNode(AArch64ISD::NEG, DL, VT, Op.getOperand(1)); in LowerVectorSRA_SRL_SHL()
7705 DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT, in LowerVectorSRA_SRL_SHL()
7721 BuildVectorSDNode *BVN = dyn_cast<BuildVectorSDNode>(RHS.getNode()); in EmitVectorComparison()
7734 Fcmeq = DAG.getNode(AArch64ISD::FCMEQz, dl, VT, LHS); in EmitVectorComparison()
7736 Fcmeq = DAG.getNode(AArch64ISD::FCMEQ, dl, VT, LHS, RHS); in EmitVectorComparison()
7737 return DAG.getNode(AArch64ISD::NOT, dl, VT, Fcmeq); in EmitVectorComparison()
7741 return DAG.getNode(AArch64ISD::FCMEQz, dl, VT, LHS); in EmitVectorComparison()
7742 return DAG.getNode(AArch64ISD::FCMEQ, dl, VT, LHS, RHS); in EmitVectorComparison()
7745 return DAG.getNode(AArch64ISD::FCMGEz, dl, VT, LHS); in EmitVectorComparison()
7746 return DAG.getNode(AArch64ISD::FCMGE, dl, VT, LHS, RHS); in EmitVectorComparison()
7749 return DAG.getNode(AArch64ISD::FCMGTz, dl, VT, LHS); in EmitVectorComparison()
7750 return DAG.getNode(AArch64ISD::FCMGT, dl, VT, LHS, RHS); in EmitVectorComparison()
7753 return DAG.getNode(AArch64ISD::FCMLEz, dl, VT, LHS); in EmitVectorComparison()
7754 return DAG.getNode(AArch64ISD::FCMGE, dl, VT, RHS, LHS); in EmitVectorComparison()
7762 return DAG.getNode(AArch64ISD::FCMLTz, dl, VT, LHS); in EmitVectorComparison()
7763 return DAG.getNode(AArch64ISD::FCMGT, dl, VT, RHS, LHS); in EmitVectorComparison()
7773 Cmeq = DAG.getNode(AArch64ISD::CMEQz, dl, VT, LHS); in EmitVectorComparison()
7775 Cmeq = DAG.getNode(AArch64ISD::CMEQ, dl, VT, LHS, RHS); in EmitVectorComparison()
7776 return DAG.getNode(AArch64ISD::NOT, dl, VT, Cmeq); in EmitVectorComparison()
7780 return DAG.getNode(AArch64ISD::CMEQz, dl, VT, LHS); in EmitVectorComparison()
7781 return DAG.getNode(AArch64ISD::CMEQ, dl, VT, LHS, RHS); in EmitVectorComparison()
7784 return DAG.getNode(AArch64ISD::CMGEz, dl, VT, LHS); in EmitVectorComparison()
7785 return DAG.getNode(AArch64ISD::CMGE, dl, VT, LHS, RHS); in EmitVectorComparison()
7788 return DAG.getNode(AArch64ISD::CMGTz, dl, VT, LHS); in EmitVectorComparison()
7789 return DAG.getNode(AArch64ISD::CMGT, dl, VT, LHS, RHS); in EmitVectorComparison()
7792 return DAG.getNode(AArch64ISD::CMLEz, dl, VT, LHS); in EmitVectorComparison()
7793 return DAG.getNode(AArch64ISD::CMGE, dl, VT, RHS, LHS); in EmitVectorComparison()
7795 return DAG.getNode(AArch64ISD::CMHS, dl, VT, RHS, LHS); in EmitVectorComparison()
7797 return DAG.getNode(AArch64ISD::CMHI, dl, VT, RHS, LHS); in EmitVectorComparison()
7800 return DAG.getNode(AArch64ISD::CMLTz, dl, VT, LHS); in EmitVectorComparison()
7801 return DAG.getNode(AArch64ISD::CMGT, dl, VT, RHS, LHS); in EmitVectorComparison()
7803 return DAG.getNode(AArch64ISD::CMHI, dl, VT, LHS, RHS); in EmitVectorComparison()
7805 return DAG.getNode(AArch64ISD::CMHS, dl, VT, LHS, RHS); in EmitVectorComparison()
7832 LHS = DAG.getNode(ISD::FP_EXTEND, dl, MVT::v4f32, LHS); in LowerVSETCC()
7833 RHS = DAG.getNode(ISD::FP_EXTEND, dl, MVT::v4f32, RHS); in LowerVSETCC()
7853 if (!Cmp.getNode()) in LowerVSETCC()
7859 if (!Cmp2.getNode()) in LowerVSETCC()
7862 Cmp = DAG.getNode(ISD::OR, dl, CmpVT, Cmp, Cmp2); in LowerVSETCC()
7876 auto Rdx = DAG.getNode(Op, DL, VecOp.getSimpleValueType(), VecOp); in getReductionSDNode()
7877 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, ScalarOp.getValueType(), Rdx, in getReductionSDNode()
7897 return DAG.getNode( in LowerVECREDUCE()
7904 return DAG.getNode( in LowerVECREDUCE()
7924 AtomicSDNode *AN = cast<AtomicSDNode>(Op.getNode()); in LowerATOMIC_LOAD_SUB()
7925 RHS = DAG.getNode(ISD::SUB, dl, VT, DAG.getConstant(0, dl, VT), RHS); in LowerATOMIC_LOAD_SUB()
7941 AtomicSDNode *AN = cast<AtomicSDNode>(Op.getNode()); in LowerATOMIC_LOAD_AND()
7942 RHS = DAG.getNode(ISD::XOR, dl, VT, DAG.getConstant(-1ULL, dl, VT), RHS); in LowerATOMIC_LOAD_AND()
7959 Size = DAG.getNode(ISD::SRL, dl, MVT::i64, Size, in LowerWindowsDYNAMIC_STACKALLOC()
7963 DAG.getNode(AArch64ISD::CALL, dl, DAG.getVTList(MVT::Other, MVT::Glue), in LowerWindowsDYNAMIC_STACKALLOC()
7971 Size = DAG.getNode(ISD::SHL, dl, MVT::i64, Size, in LowerWindowsDYNAMIC_STACKALLOC()
7983 SDNode *Node = Op.getNode(); in LowerDYNAMIC_STACKALLOC()
7993 SP = DAG.getNode(ISD::SUB, dl, MVT::i64, SP, Size); in LowerDYNAMIC_STACKALLOC()
7995 SP = DAG.getNode(ISD::AND, dl, VT, SP.getValue(0), in LowerDYNAMIC_STACKALLOC()
8008 SP = DAG.getNode(ISD::SUB, dl, MVT::i64, SP, Size); in LowerDYNAMIC_STACKALLOC()
8010 SP = DAG.getNode(ISD::AND, dl, VT, SP.getValue(0), in LowerDYNAMIC_STACKALLOC()
8743 N = N->getOperand(0).getNode(); in isDesirableToCommuteWithShift()
8804 !ISD::isBuildVectorAllOnes(Ones.getNode())) in foldVectorXorShiftIntoCmp()
8813 return DAG.getNode(AArch64ISD::CMGEz, SDLoc(N), VT, Shift.getOperand(0)); in foldVectorXorShiftIntoCmp()
8831 SDValue Neg = DAG.getNode(ISD::SUB, DL, VT, DAG.getConstant(0, DL, VT), in performIntegerAbsCombine()
8835 DAG.getNode(AArch64ISD::SUBS, DL, DAG.getVTList(VT, MVT::i32), in performIntegerAbsCombine()
8837 return DAG.getNode(AArch64ISD::CSEL, DL, VT, N0.getOperand(0), Neg, in performIntegerAbsCombine()
8839 SDValue(Cmp.getNode(), 1)); in performIntegerAbsCombine()
8879 SDValue Add = DAG.getNode(ISD::ADD, DL, VT, N0, Pow2MinusOne); in BuildSDIVPow2()
8880 SDValue CSel = DAG.getNode(AArch64ISD::CSEL, DL, VT, Add, N0, CCVal, Cmp); in BuildSDIVPow2()
8882 Created.push_back(Cmp.getNode()); in BuildSDIVPow2()
8883 Created.push_back(Add.getNode()); in BuildSDIVPow2()
8884 Created.push_back(CSel.getNode()); in BuildSDIVPow2()
8888 DAG.getNode(ISD::SRA, DL, VT, CSel, DAG.getConstant(Lg2, DL, MVT::i64)); in BuildSDIVPow2()
8895 Created.push_back(SRA.getNode()); in BuildSDIVPow2()
8896 return DAG.getNode(ISD::SUB, DL, VT, DAG.getConstant(0, DL, VT), SRA); in BuildSDIVPow2()
8929 if (N0->hasOneUse() && (isSignExtended(N0.getNode(), DAG) || in performMulCombine()
8930 isZeroExtended(N0.getNode(), DAG))) in performMulCombine()
8981 SDValue ShiftedVal = DAG.getNode(ISD::SHL, DL, VT, N0, in performMulCombine()
8986 SDValue Res = DAG.getNode(AddSubOpc, DL, VT, AddSubN0, AddSubN1); in performMulCombine()
8991 return DAG.getNode(ISD::SUB, DL, VT, DAG.getConstant(0, DL, VT), Res); in performMulCombine()
8994 return DAG.getNode(ISD::SHL, DL, VT, Res, in performMulCombine()
9033 SDValue SourceConst = DAG.getNode(N->getOpcode(), DL, VT, SDValue(BV, 0)); in performVectorCompareAndMaskUnaryOpCombine()
9035 SDValue MaskConst = DAG.getNode(ISD::BITCAST, DL, IntVT, SourceConst); in performVectorCompareAndMaskUnaryOpCombine()
9036 SDValue NewAnd = DAG.getNode(ISD::AND, DL, IntVT, in performVectorCompareAndMaskUnaryOpCombine()
9038 SDValue Res = DAG.getNode(ISD::BITCAST, DL, VT, NewAnd); in performVectorCompareAndMaskUnaryOpCombine()
9064 if (Subtarget->hasNEON() && ISD::isNormalLoad(N0.getNode()) && N0.hasOneUse() && in performIntToFpCombine()
9078 return DAG.getNode(Opcode, SDLoc(N), VT, Load); in performIntToFpCombine()
9146 DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, ResTy, in performFpToIntCombine()
9151 FixConv = DAG.getNode(ISD::TRUNCATE, DL, N->getValueType(0), FixConv); in performFpToIntCombine()
9215 ConvInput = DAG.getNode(IsSigned ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND, DL, in performFDivCombine()
9220 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, Op.getValueType(), in performFDivCombine()
9285 return DAG.getNode(AArch64ISD::EXTR, DL, VT, LHS, RHS, in tryCombineToEXTR()
9329 return DAG.getNode(AArch64ISD::BSL, DL, VT, SDValue(BVN0, 0), in tryCombineToBSL()
9373 return DAG.getNode(ISD::ROTR, DL, VT, N0, N1); in performSRLCombine()
9376 return DAG.getNode(ISD::ROTR, DL, VT, N0, N1); in performSRLCombine()
9441 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, VT, Source, HalfIdx); in performBitcastCombine()
9482 return DAG.getNode(ISD::TRUNCATE, dl, VT, in performConcatVectorsCombine()
9485 DAG.getNode(ISD::BITCAST, dl, MidVT, N00), in performConcatVectorsCombine()
9486 DAG.getNode(ISD::BITCAST, dl, MidVT, N10), Mask)); in performConcatVectorsCombine()
9500 return DAG.getNode(AArch64ISD::DUPLANE64, dl, VT, WidenVector(N0, DAG), in performConcatVectorsCombine()
9526 return DAG.getNode(ISD::BITCAST, dl, VT, in performConcatVectorsCombine()
9527 DAG.getNode(ISD::CONCAT_VECTORS, dl, ConcatTy, in performConcatVectorsCombine()
9528 DAG.getNode(ISD::BITCAST, dl, RHSTy, N0), in performConcatVectorsCombine()
9573 DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VecResTy, IID, Vec, Shift); in tryCombineFixedPointConvert()
9574 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, ResTy, Convert, Lane); in tryCombineFixedPointConvert()
9624 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, NarrowTy, in tryExtendDUPToExtractHigh()
9625 DAG.getNode(N->getOpcode(), dl, NewVT, N->ops()), in tryExtendDUPToExtractHigh()
9761 LHS = DAG.getNode(ISD::ADD, dl, VT, RHS, DAG.getConstant(1, dl, VT)); in performSetccAddFolding()
9762 return DAG.getNode(AArch64ISD::CSEL, dl, VT, RHS, LHS, CCVal, Cmp); in performSetccAddFolding()
9803 if (!RHS.getNode()) in performAddSubLongCombine()
9806 RHS = DAG.getNode(ExtType, SDLoc(N), VT, RHS); in performAddSubLongCombine()
9809 if (!LHS.getNode()) in performAddSubLongCombine()
9812 LHS = DAG.getNode(ExtType, SDLoc(N), VT, LHS); in performAddSubLongCombine()
9815 return DAG.getNode(N->getOpcode(), SDLoc(N), VT, LHS, RHS); in performAddSubLongCombine()
9842 if (!RHS.getNode()) in tryCombineLongOpWithDup()
9846 if (!LHS.getNode()) in tryCombineLongOpWithDup()
9850 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, SDLoc(N), N->getValueType(0), in tryCombineLongOpWithDup()
9903 return DAG.getNode(Opcode, dl, N->getValueType(0), N->getOperand(1), in tryCombineShiftImm()
9907 return DAG.getNode(Opcode, dl, N->getValueType(0), N->getOperand(1), in tryCombineShiftImm()
9926 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, SDLoc(N), MVT::i32, in tryCombineCRC32()
9933 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, N->getValueType(0), in combineAcrossLanesIntrinsic()
9934 DAG.getNode(Opc, dl, in combineAcrossLanesIntrinsic()
9964 return DAG.getNode(ISD::FMAXIMUM, SDLoc(N), N->getValueType(0), in performIntrinsicCombine()
9967 return DAG.getNode(ISD::FMINIMUM, SDLoc(N), N->getValueType(0), in performIntrinsicCombine()
9970 return DAG.getNode(ISD::FMAXNUM, SDLoc(N), N->getValueType(0), in performIntrinsicCombine()
9973 return DAG.getNode(ISD::FMINNUM, SDLoc(N), N->getValueType(0), in performIntrinsicCombine()
10005 SDNode *ABDNode = N->getOperand(0).getNode(); in performExtendCombine()
10010 if (!NewABD.getNode()) in performExtendCombine()
10013 return DAG.getNode(ISD::ZERO_EXTEND, SDLoc(N), N->getValueType(0), in performExtendCombine()
10069 Src = DAG.getNode(N->getOpcode(), DL, SrcVT, Src); in performExtendCombine()
10082 Lo = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, InNVT, Src, in performExtendCombine()
10084 Hi = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, InNVT, Src, in performExtendCombine()
10086 Lo = DAG.getNode(N->getOpcode(), DL, LoVT, Lo); in performExtendCombine()
10087 Hi = DAG.getNode(N->getOpcode(), DL, HiVT, Hi); in performExtendCombine()
10091 return DAG.getNode(ISD::CONCAT_VECTORS, DL, ResVT, Lo, Hi); in performExtendCombine()
10124 DAG.getNode(ISD::ADD, DL, MVT::i64, BasePtr, in splitStoreSplat()
10320 SDValue SubVector0 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, HalfVT, StVal, in splitStores()
10322 SDValue SubVector1 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, HalfVT, StVal, in splitStores()
10328 SDValue OffsetPtr = DAG.getNode(ISD::ADD, DL, MVT::i64, BasePtr, in splitStores()
10347 SDNode *LD = N->getOperand(LoadIdx).getNode(); in performPostLD1Combine()
10380 for (SDNode::use_iterator UI = Addr.getNode()->use_begin(), UE = in performPostLD1Combine()
10381 Addr.getNode()->use_end(); UI != UE; ++UI) { in performPostLD1Combine()
10389 if (ConstantSDNode *CInc = dyn_cast<ConstantSDNode>(Inc.getNode())) { in performPostLD1Combine()
10404 Worklist.push_back(Vector.getNode()); in performPostLD1Combine()
10428 SDValue(UpdN.getNode(), 2) // Chain in performPostLD1Combine()
10431 DCI.CombineTo(N, SDValue(UpdN.getNode(), 0)); // Dup/Inserted Result in performPostLD1Combine()
10432 DCI.CombineTo(User, SDValue(UpdN.getNode(), 1)); // Write back register in performPostLD1Combine()
10483 for (SDNode::use_iterator UI = Addr.getNode()->use_begin(), in performNEONPostLDSTCombine()
10484 UE = Addr.getNode()->use_end(); UI != UE; ++UI) { in performNEONPostLDSTCombine()
10494 Visited.insert(Addr.getNode()); in performNEONPostLDSTCombine()
10562 if (ConstantSDNode *CInc = dyn_cast<ConstantSDNode>(Inc.getNode())) { in performNEONPostLDSTCombine()
10598 NewResults.push_back(SDValue(UpdN.getNode(), i)); in performNEONPostLDSTCombine()
10600 NewResults.push_back(SDValue(UpdN.getNode(), NumResultVecs + 1)); in performNEONPostLDSTCombine()
10602 DCI.CombineTo(User, SDValue(UpdN.getNode(), NumResultVecs)); in performNEONPostLDSTCombine()
10614 switch(V.getNode()->getOpcode()) { in checkValueWidth()
10618 LoadSDNode *LoadNode = cast<LoadSDNode>(V.getNode()); in checkValueWidth()
10627 VTSDNode *TypeNode = cast<VTSDNode>(V.getNode()->getOperand(1)); in checkValueWidth()
10636 VTSDNode *TypeNode = cast<VTSDNode>(V.getNode()->getOperand(1)); in checkValueWidth()
10646 return std::abs(cast<ConstantSDNode>(V.getNode())->getSExtValue()) < in checkValueWidth()
10796 SDNode *SubsNode = N->getOperand(CmpIndex).getNode(); in performCONDCombine()
10805 SDNode *AndNode = SubsNode->getOperand(0).getNode(); in performCONDCombine()
10829 SDValue AddInputValue1 = AddValue.getNode()->getOperand(0); in performCONDCombine()
10830 SDValue AddInputValue2 = AddValue.getNode()->getOperand(1); in performCONDCombine()
10836 if (!isa<ConstantSDNode>(AddInputValue2.getNode()) || in performCONDCombine()
10837 !isa<ConstantSDNode>(SubsInputValue.getNode())) in performCONDCombine()
10848 cast<ConstantSDNode>(AddInputValue2.getNode())->getSExtValue(), in performCONDCombine()
10849 cast<ConstantSDNode>(SubsInputValue.getNode())->getSExtValue())) in performCONDCombine()
10858 SDValue NewValue = DAG.getNode(CondOpcode, SDLoc(SubsNode), VTs, Ops); in performCONDCombine()
10859 DAG.ReplaceAllUsesWith(SubsNode, NewValue.getNode()); in performCONDCombine()
10876 N = NV.getNode(); in performBRCONDCombine()
10917 BR = DAG.getNode(AArch64ISD::CBZ, SDLoc(N), MVT::Other, Chain, LHS, Dest); in performBRCONDCombine()
10919 BR = DAG.getNode(AArch64ISD::CBNZ, SDLoc(N), MVT::Other, Chain, LHS, Dest); in performBRCONDCombine()
11020 return DAG.getNode(NewOpc, DL, MVT::Other, N->getOperand(0), NewTestSrc, in performTBZCombine()
11050 return DAG.getNode(ISD::VSELECT, SDLoc(N), ResVT, SetCC, in performVSelectCombine()
11104 DAG.getNode(ISD::SCALAR_TO_VECTOR, DL, SrcVT, N0.getOperand(0)); in performSelectCombine()
11106 DAG.getNode(ISD::SCALAR_TO_VECTOR, DL, SrcVT, N0.getOperand(1)); in performSelectCombine()
11107 SDValue SetCC = DAG.getNode(ISD::SETCC, DL, CCVT, LHS, RHS, N0.getOperand(2)); in performSelectCombine()
11112 Mask = DAG.getNode(ISD::BITCAST, DL, in performSelectCombine()
11175 return DAG.getNode(ISD::SUB, DL, MVT::i64, Result, in performGlobalAddressCombine()
11358 if (!getIndexedAddressParts(Ptr.getNode(), Base, Offset, AM, IsInc, DAG)) in getPreIndexedAddressParts()
11402 Op = DAG.getNode(ISD::BITCAST, DL, MVT::i32, Op); in ReplaceBITCASTResults()
11403 Results.push_back(DAG.getNode(ISD::TRUNCATE, DL, MVT::i16, Op)); in ReplaceBITCASTResults()
11415 SDValue InterVal = DAG.getNode(InterOp, dl, LoVT, Lo, Hi); in ReplaceReductionResults()
11416 SDValue SplitVal = DAG.getNode(AcrossOp, dl, LoVT, InterVal); in ReplaceReductionResults()
11422 SDValue Lo = DAG.getNode(ISD::TRUNCATE, DL, MVT::i64, N); in splitInt128()
11423 SDValue Hi = DAG.getNode(ISD::TRUNCATE, DL, MVT::i64, in splitInt128()
11424 DAG.getNode(ISD::SRL, DL, MVT::i128, N, in splitInt128()
11431 SDLoc dl(V.getNode()); in createGPRPairNode()
11434 DAG.getNode(ISD::SRL, dl, MVT::i128, V, DAG.getConstant(64, dl, MVT::i64)), in createGPRPairNode()