Lines Matching refs:getNode
491 assert((!Result.getNode() || in LowerOperation()
492 Result.getNode()->getNumValues() == 2) && in LowerOperation()
517 return DAG.getNode(AMDGPUISD::R600_EXPORT, DL, Op.getValueType(), Args); in LowerOperation()
567 return DAG.getNode(AMDGPUISD::TEXTURE_FETCH, DL, MVT::v4f32, TexArgs); in LowerOperation()
571 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::f32, Op.getOperand(1), in LowerOperation()
573 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::f32, Op.getOperand(2), in LowerOperation()
575 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::f32, Op.getOperand(1), in LowerOperation()
577 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::f32, Op.getOperand(2), in LowerOperation()
579 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::f32, Op.getOperand(1), in LowerOperation()
581 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::f32, Op.getOperand(2), in LowerOperation()
583 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::f32, Op.getOperand(1), in LowerOperation()
585 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::f32, Op.getOperand(2), in LowerOperation()
588 return DAG.getNode(AMDGPUISD::DOT4, DL, MVT::f32, Args); in LowerOperation()
635 return DAG.getNode(AMDGPUISD::RSQ, DL, VT, Op.getOperand(1)); in LowerOperation()
638 return DAG.getNode(AMDGPUISD::RSQ_CLAMP, DL, VT, Op.getOperand(1)); in LowerOperation()
700 Args.push_back(DAG.getNode( in vectorToVerticalVector()
705 return DAG.getNode(AMDGPUISD::BUILD_VERTICAL_VECTOR, DL, VecVT, Args); in vectorToVerticalVector()
719 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, Op.getValueType(), in LowerEXTRACT_VECTOR_ELT()
735 SDValue Insert = DAG.getNode(ISD::INSERT_VECTOR_ELT, DL, Op.getValueType(), in LowerINSERT_VECTOR_ELT()
752 return DAG.getNode(AMDGPUISD::CONST_DATA_PTR, SDLoc(GSD), ConstPtrVT, GA); in LowerGlobalAddress()
763 SDValue FractPart = DAG.getNode(AMDGPUISD::FRACT, DL, VT, in LowerTrig()
764 DAG.getNode(ISD::FADD, DL, VT, in LowerTrig()
765 DAG.getNode(ISD::FMUL, DL, VT, Arg, in LowerTrig()
779 SDValue TrigVal = DAG.getNode(TrigNode, DL, VT, in LowerTrig()
780 DAG.getNode(ISD::FADD, DL, VT, FractPart, in LowerTrig()
785 return DAG.getNode(ISD::FMUL, DL, VT, TrigVal, in LowerTrig()
801 SDValue BigShift = DAG.getNode(ISD::SUB, DL, VT, Shift, Width); in LowerSHLParts()
802 SDValue CompShift = DAG.getNode(ISD::SUB, DL, VT, Width1, Shift); in LowerSHLParts()
809 SDValue Overflow = DAG.getNode(ISD::SRL, DL, VT, Lo, CompShift); in LowerSHLParts()
810 Overflow = DAG.getNode(ISD::SRL, DL, VT, Overflow, One); in LowerSHLParts()
812 SDValue HiSmall = DAG.getNode(ISD::SHL, DL, VT, Hi, Shift); in LowerSHLParts()
813 HiSmall = DAG.getNode(ISD::OR, DL, VT, HiSmall, Overflow); in LowerSHLParts()
814 SDValue LoSmall = DAG.getNode(ISD::SHL, DL, VT, Lo, Shift); in LowerSHLParts()
816 SDValue HiBig = DAG.getNode(ISD::SHL, DL, VT, Lo, BigShift); in LowerSHLParts()
822 return DAG.getNode(ISD::MERGE_VALUES, DL, DAG.getVTList(VT,VT), Lo, Hi); in LowerSHLParts()
839 SDValue BigShift = DAG.getNode(ISD::SUB, DL, VT, Shift, Width); in LowerSRXParts()
840 SDValue CompShift = DAG.getNode(ISD::SUB, DL, VT, Width1, Shift); in LowerSRXParts()
847 SDValue Overflow = DAG.getNode(ISD::SHL, DL, VT, Hi, CompShift); in LowerSRXParts()
848 Overflow = DAG.getNode(ISD::SHL, DL, VT, Overflow, One); in LowerSRXParts()
850 SDValue HiSmall = DAG.getNode(SRA ? ISD::SRA : ISD::SRL, DL, VT, Hi, Shift); in LowerSRXParts()
851 SDValue LoSmall = DAG.getNode(ISD::SRL, DL, VT, Lo, Shift); in LowerSRXParts()
852 LoSmall = DAG.getNode(ISD::OR, DL, VT, LoSmall, Overflow); in LowerSRXParts()
854 SDValue LoBig = DAG.getNode(SRA ? ISD::SRA : ISD::SRL, DL, VT, Hi, BigShift); in LowerSRXParts()
855 SDValue HiBig = SRA ? DAG.getNode(ISD::SRA, DL, VT, Hi, Width1) : Zero; in LowerSRXParts()
860 return DAG.getNode(ISD::MERGE_VALUES, DL, DAG.getVTList(VT,VT), Lo, Hi); in LowerSRXParts()
871 SDValue OVF = DAG.getNode(ovf, DL, VT, Lo, Hi); in LowerUADDSUBO()
873 OVF = DAG.getNode(ISD::SIGN_EXTEND_INREG, DL, VT, OVF, in LowerUADDSUBO()
876 SDValue Res = DAG.getNode(mainop, DL, VT, Lo, Hi); in LowerUADDSUBO()
878 return DAG.getNode(ISD::MERGE_VALUES, DL, DAG.getVTList(VT, VT), Res, OVF); in LowerUADDSUBO()
883 return DAG.getNode( in lowerFP_TO_UINT()
893 return DAG.getNode( in lowerFP_TO_SINT()
993 return DAG.getNode(ISD::SELECT_CC, DL, VT, LHS, RHS, True, False, CC); in LowerSELECT_CC()
1034 True = DAG.getNode(ISD::BITCAST, DL, CompareVT, True); in LowerSELECT_CC()
1035 False = DAG.getNode(ISD::BITCAST, DL, CompareVT, False); in LowerSELECT_CC()
1050 SDValue SelectNode = DAG.getNode(ISD::SELECT_CC, DL, CompareVT, in LowerSELECT_CC()
1054 return DAG.getNode(ISD::BITCAST, DL, VT, SelectNode); in LowerSELECT_CC()
1074 SDValue Cond = DAG.getNode(ISD::SELECT_CC, DL, CompareVT, LHS, RHS, HWTrue, HWFalse, CC); in LowerSELECT_CC()
1076 return DAG.getNode(ISD::SELECT_CC, DL, VT, in LowerSELECT_CC()
1105 return DAG.getNode(ISD::SRL, DL, Ptr.getValueType(), Ptr, in stackPtrToRegIndex()
1167 LoadPtr = DAG.getNode(ISD::ADD, DL, MVT::i32, BasePtr, Offset); in lowerPrivateTruncStore()
1172 SDValue Ptr = DAG.getNode(ISD::AND, DL, MVT::i32, LoadPtr, in lowerPrivateTruncStore()
1184 SDValue ByteIdx = DAG.getNode(ISD::AND, DL, MVT::i32, LoadPtr, in lowerPrivateTruncStore()
1188 SDValue ShiftAmt = DAG.getNode(ISD::SHL, DL, MVT::i32, ByteIdx, in lowerPrivateTruncStore()
1193 SDValue SExtValue = DAG.getNode(ISD::SIGN_EXTEND, DL, MVT::i32, in lowerPrivateTruncStore()
1200 SDValue ShiftedValue = DAG.getNode(ISD::SHL, DL, MVT::i32, in lowerPrivateTruncStore()
1204 SDValue DstMask = DAG.getNode(ISD::SHL, DL, MVT::i32, Mask, ShiftAmt); in lowerPrivateTruncStore()
1211 Dst = DAG.getNode(ISD::AND, DL, MVT::i32, Dst, DstMask); in lowerPrivateTruncStore()
1214 SDValue Value = DAG.getNode(ISD::OR, DL, MVT::i32, Dst, ShiftedValue); in lowerPrivateTruncStore()
1223 Chain = DAG.getNode(AMDGPUISD::DUMMY_CHAIN, DL, MVT::Other, NewStore); in lowerPrivateTruncStore()
1249 SDValue NewChain = DAG.getNode(AMDGPUISD::DUMMY_CHAIN, DL, MVT::Other, Chain); in LowerSTORE()
1267 SDValue DWordAddr = DAG.getNode(ISD::SRL, DL, PtrVT, Ptr, in LowerSTORE()
1284 SDValue ByteIndex = DAG.getNode(ISD::AND, DL, PtrVT, Ptr, in LowerSTORE()
1286 SDValue BitShift = DAG.getNode(ISD::SHL, DL, VT, ByteIndex, in LowerSTORE()
1290 SDValue Mask = DAG.getNode(ISD::SHL, DL, VT, MaskConstant, BitShift); in LowerSTORE()
1293 SDValue TruncValue = DAG.getNode(ISD::AND, DL, VT, Value, MaskConstant); in LowerSTORE()
1294 SDValue ShiftedValue = DAG.getNode(ISD::SHL, DL, VT, TruncValue, BitShift); in LowerSTORE()
1311 Ptr = DAG.getNode(AMDGPUISD::DWORDADDR, DL, PtrVT, DWordAddr); in LowerSTORE()
1332 Ptr = DAG.getNode(AMDGPUISD::DWORDADDR, DL, PtrVT, DWordAddr); in LowerSTORE()
1395 LoadPtr = DAG.getNode(ISD::ADD, DL, MVT::i32, BasePtr, Offset); in lowerPrivateExtLoad()
1400 SDValue Ptr = DAG.getNode(ISD::AND, DL, MVT::i32, LoadPtr, in lowerPrivateExtLoad()
1410 SDValue ByteIdx = DAG.getNode(ISD::AND, DL, MVT::i32, in lowerPrivateExtLoad()
1414 SDValue ShiftAmt = DAG.getNode(ISD::SHL, DL, MVT::i32, ByteIdx, in lowerPrivateExtLoad()
1418 SDValue Ret = DAG.getNode(ISD::SRL, DL, MVT::i32, Read, ShiftAmt); in lowerPrivateExtLoad()
1425 Ret = DAG.getNode(ISD::SIGN_EXTEND_INREG, DL, MVT::i32, Ret, MemEltVTNode); in lowerPrivateExtLoad()
1472 Result = DAG.getNode(AMDGPUISD::CONST_ADDRESS, DL, MVT::v4i32, in LowerLOAD()
1473 DAG.getNode(ISD::SRL, DL, MVT::i32, Ptr, in LowerLOAD()
1481 Result = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::i32, Result, in LowerLOAD()
1505 SDValue Res = DAG.getNode(ISD::SIGN_EXTEND_INREG, DL, VT, NewLoad, in LowerLOAD()
1519 Ptr = DAG.getNode(ISD::SRL, DL, MVT::i32, Ptr, DAG.getConstant(2, DL, MVT::i32)); in LowerLOAD()
1520 Ptr = DAG.getNode(AMDGPUISD::DWORDADDR, DL, MVT::i32, Ptr); in LowerLOAD()
1531 return DAG.getNode(AMDGPUISD::BRANCH_COND, SDLoc(Op), Op.getValueType(), in LowerBRCOND()
1695 NewBldVec[i] = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, EltTy, VectorEntry, in CompactSwizzlableVector()
1739 NewBldVec[i] = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, EltTy, VectorEntry, in ReorganizeVector()
1817 SDValue NewPtr = DAG.getNode(ISD::ADD, DL, Ptr.getValueType(), Ptr, in constBufferLoad()
1819 Slots[i] = DAG.getNode(AMDGPUISD::CONST_ADDRESS, DL, MVT::i32, NewPtr); in constBufferLoad()
1829 Result = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::i32, Result, in constBufferLoad()
1853 return DAG.getNode(ISD::UINT_TO_FP, DL, N->getValueType(0), in PerformDAGCombine()
1878 return DAG.getNode(ISD::SELECT_CC, DL, N->getValueType(0), in PerformDAGCombine()
1915 Ops.append(InVec.getNode()->op_begin(), in PerformDAGCombine()
1916 InVec.getNode()->op_end()); in PerformDAGCombine()
1931 DAG.getNode(ISD::ANY_EXTEND, DL, OpVT, InVal) : in PerformDAGCombine()
1932 DAG.getNode(ISD::TRUNCATE, DL, OpVT, InVal); in PerformDAGCombine()
1956 return DAG.getNode(ISD::BITCAST, DL, N->getVTList(), in PerformDAGCombine()
1983 if (LHS.getOperand(2).getNode() != True.getNode() || in PerformDAGCombine()
1984 LHS.getOperand(3).getNode() != False.getNode() || in PerformDAGCombine()
1985 RHS.getNode() != False.getNode()) { in PerformDAGCombine()
2026 return DAG.getNode(AMDGPUISD::R600_EXPORT, DL, N->getVTList(), NewArgs); in PerformDAGCombine()
2055 return DAG.getNode(AMDGPUISD::TEXTURE_FETCH, DL, N->getVTList(), NewArgs); in PerformDAGCombine()
2083 if (!Neg.getNode()) in FoldOperand()
2089 if (!Abs.getNode()) in FoldOperand()
2098 if (!Sel.getNode()) in FoldOperand()
2188 if (!Imm.getNode()) in FoldOperand()