1040   return DAG.getNode(AMDGPUISD::ENDPGM, DL, MVT::Other, Chain);  in LowerReturn()
1072   for (SDNode::use_iterator U = DAG.getEntryNode().getNode()->use_begin(),  in addTokenForArgument()
1073                             UE = DAG.getEntryNode().getNode()->use_end();  in addTokenForArgument()
1091   return DAG.getNode(ISD::TokenFactor, SDLoc(Chain), MVT::Other, ArgChains);  in addTokenForArgument()
1245     SDValue Lo = DAG.getNode(ISD::BITCAST, SL, MVT::i32, Op.getOperand(0));  in LowerCONCAT_VECTORS()
1246     SDValue Hi = DAG.getNode(ISD::BITCAST, SL, MVT::i32, Op.getOperand(1));  in LowerCONCAT_VECTORS()
1249     return DAG.getNode(ISD::BITCAST, SL, VT, BV);  in LowerCONCAT_VECTORS()
1298       return DAG.getNode(AMDGPUISD::FMIN_LEGACY, DL, VT, RHS, LHS);  in combineFMinMaxLegacy()
1299     return DAG.getNode(AMDGPUISD::FMAX_LEGACY, DL, VT, LHS, RHS);  in combineFMinMaxLegacy()
1317       return DAG.getNode(AMDGPUISD::FMIN_LEGACY, DL, VT, LHS, RHS);  in combineFMinMaxLegacy()
1318     return DAG.getNode(AMDGPUISD::FMAX_LEGACY, DL, VT, RHS, LHS);  in combineFMinMaxLegacy()
1323       return DAG.getNode(AMDGPUISD::FMAX_LEGACY, DL, VT, RHS, LHS);  in combineFMinMaxLegacy()
1324     return DAG.getNode(AMDGPUISD::FMIN_LEGACY, DL, VT, LHS, RHS);  in combineFMinMaxLegacy()
1335       return DAG.getNode(AMDGPUISD::FMAX_LEGACY, DL, VT, LHS, RHS);  in combineFMinMaxLegacy()
1336     return DAG.getNode(AMDGPUISD::FMIN_LEGACY, DL, VT, RHS, LHS);  in combineFMinMaxLegacy()
1348   SDValue Vec = DAG.getNode(ISD::BITCAST, SL, MVT::v2i32, Op);  in split64BitValue()
1353   SDValue Lo = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, SL, MVT::i32, Vec, Zero);  in split64BitValue()
1354   SDValue Hi = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, SL, MVT::i32, Vec, One);  in split64BitValue()
1362   SDValue Vec = DAG.getNode(ISD::BITCAST, SL, MVT::v2i32, Op);  in getLoHalf64()
1364   return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, SL, MVT::i32, Vec, Zero);  in getLoHalf64()
1370   SDValue Vec = DAG.getNode(ISD::BITCAST, SL, MVT::v2i32, Op);  in getHiHalf64()
1372   return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, SL, MVT::i32, Vec, One);  in getHiHalf64()
1414     DAG.getNode(ISD::CONCAT_VECTORS, SL, VT, LoLoad, HiLoad),  in SplitVectorLoad()
1415     DAG.getNode(ISD::TokenFactor, SL, MVT::Other,  in SplitVectorLoad()
1460   return DAG.getNode(ISD::TokenFactor, SL, MVT::Other, LoStore, HiStore);  in SplitVectorStore()
1496     jq = DAG.getNode(ISD::XOR, DL, VT, LHS, RHS);  in LowerDIVREM24()
1499     jq = DAG.getNode(ISD::SRA, DL, VT, jq,  in LowerDIVREM24()
1503     jq = DAG.getNode(ISD::OR, DL, VT, jq, DAG.getConstant(1, DL, VT));  in LowerDIVREM24()
1513   SDValue fa = DAG.getNode(ToFp, DL, FltVT, ia);  in LowerDIVREM24()
1516   SDValue fb = DAG.getNode(ToFp, DL, FltVT, ib);  in LowerDIVREM24()
1518   SDValue fq = DAG.getNode(ISD::FMUL, DL, FltVT,  in LowerDIVREM24()
1519                            fa, DAG.getNode(AMDGPUISD::RCP, DL, FltVT, fb));  in LowerDIVREM24()
1522   fq = DAG.getNode(ISD::FTRUNC, DL, FltVT, fq);  in LowerDIVREM24()
1525   SDValue fqneg = DAG.getNode(ISD::FNEG, DL, FltVT, fq);  in LowerDIVREM24()
1531   SDValue fr = DAG.getNode(OpCode, DL, FltVT, fqneg, fb, fa);  in LowerDIVREM24()
1534   SDValue iq = DAG.getNode(ToInt, DL, IntVT, fq);  in LowerDIVREM24()
1537   fr = DAG.getNode(ISD::FABS, DL, FltVT, fr);  in LowerDIVREM24()
1540   fb = DAG.getNode(ISD::FABS, DL, FltVT, fb);  in LowerDIVREM24()
1548   jq = DAG.getNode(ISD::SELECT, DL, VT, cv, jq, DAG.getConstant(0, DL, VT));  in LowerDIVREM24()
1551   SDValue Div = DAG.getNode(ISD::ADD, DL, VT, iq, jq);  in LowerDIVREM24()
1554   SDValue Rem = DAG.getNode(ISD::MUL, DL, VT, Div, RHS);  in LowerDIVREM24()
1555   Rem = DAG.getNode(ISD::SUB, DL, VT, LHS, Rem);  in LowerDIVREM24()
1561     Div = DAG.getNode(ISD::SIGN_EXTEND_INREG, DL, VT, Div, InRegSize);  in LowerDIVREM24()
1562     Rem = DAG.getNode(ISD::SIGN_EXTEND_INREG, DL, VT, Rem, InRegSize);  in LowerDIVREM24()
1565     Div = DAG.getNode(ISD::AND, DL, VT, Div, TruncMask);  in LowerDIVREM24()
1566     Rem = DAG.getNode(ISD::AND, DL, VT, Rem, TruncMask);  in LowerDIVREM24()
1587   SDValue LHS_Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, HalfVT, LHS, Zero);  in LowerUDIVREM64()
1588   SDValue LHS_Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, HalfVT, LHS, One);  in LowerUDIVREM64()
1591   SDValue RHS_Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, HalfVT, RHS, Zero);  in LowerUDIVREM64()
1592   SDValue RHS_Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, HalfVT, RHS, One);  in LowerUDIVREM64()
1597     SDValue Res = DAG.getNode(ISD::UDIVREM, DL, DAG.getVTList(HalfVT, HalfVT),  in LowerUDIVREM64()
1603     Results.push_back(DAG.getNode(ISD::BITCAST, DL, MVT::i64, DIV));  in LowerUDIVREM64()
1604     Results.push_back(DAG.getNode(ISD::BITCAST, DL, MVT::i64, REM));  in LowerUDIVREM64()
1614     SDValue Cvt_Lo = DAG.getNode(ISD::UINT_TO_FP, DL, MVT::f32, RHS_Lo);  in LowerUDIVREM64()
1615     SDValue Cvt_Hi = DAG.getNode(ISD::UINT_TO_FP, DL, MVT::f32, RHS_Hi);  in LowerUDIVREM64()
1616     SDValue Mad1 = DAG.getNode(FMAD, DL, MVT::f32, Cvt_Hi,  in LowerUDIVREM64()
1619     SDValue Rcp = DAG.getNode(AMDGPUISD::RCP, DL, MVT::f32, Mad1);  in LowerUDIVREM64()
1620     SDValue Mul1 = DAG.getNode(ISD::FMUL, DL, MVT::f32, Rcp,  in LowerUDIVREM64()
1622     SDValue Mul2 = DAG.getNode(ISD::FMUL, DL, MVT::f32, Mul1,  in LowerUDIVREM64()
1624     SDValue Trunc = DAG.getNode(ISD::FTRUNC, DL, MVT::f32, Mul2);  in LowerUDIVREM64()
1625     SDValue Mad2 = DAG.getNode(FMAD, DL, MVT::f32, Trunc,  in LowerUDIVREM64()
1628     SDValue Rcp_Lo = DAG.getNode(ISD::FP_TO_UINT, DL, HalfVT, Mad2);  in LowerUDIVREM64()
1629     SDValue Rcp_Hi = DAG.getNode(ISD::FP_TO_UINT, DL, HalfVT, Trunc);  in LowerUDIVREM64()
1638     SDValue Neg_RHS = DAG.getNode(ISD::SUB, DL, VT, Zero64, RHS);  in LowerUDIVREM64()
1639     SDValue Mullo1 = DAG.getNode(ISD::MUL, DL, VT, Neg_RHS, Rcp64);  in LowerUDIVREM64()
1640     SDValue Mulhi1 = DAG.getNode(ISD::MULHU, DL, VT, Rcp64, Mullo1);  in LowerUDIVREM64()
1641     SDValue Mulhi1_Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, HalfVT, Mulhi1,  in LowerUDIVREM64()
1643     SDValue Mulhi1_Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, HalfVT, Mulhi1,  in LowerUDIVREM64()
1646     SDValue Add1_Lo = DAG.getNode(ISD::ADDCARRY, DL, HalfCarryVT, Rcp_Lo,  in LowerUDIVREM64()
1648     SDValue Add1_Hi = DAG.getNode(ISD::ADDCARRY, DL, HalfCarryVT, Rcp_Hi,  in LowerUDIVREM64()
1650     SDValue Add1_HiNc = DAG.getNode(ISD::ADD, DL, HalfVT, Rcp_Hi, Mulhi1_Hi);  in LowerUDIVREM64()
1654     SDValue Mullo2 = DAG.getNode(ISD::MUL, DL, VT, Neg_RHS, Add1);  in LowerUDIVREM64()
1655     SDValue Mulhi2 = DAG.getNode(ISD::MULHU, DL, VT, Add1, Mullo2);  in LowerUDIVREM64()
1656     SDValue Mulhi2_Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, HalfVT, Mulhi2,  in LowerUDIVREM64()
1658     SDValue Mulhi2_Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, HalfVT, Mulhi2,  in LowerUDIVREM64()
1661     SDValue Add2_Lo = DAG.getNode(ISD::ADDCARRY, DL, HalfCarryVT, Add1_Lo,  in LowerUDIVREM64()
1663     SDValue Add2_HiC = DAG.getNode(ISD::ADDCARRY, DL, HalfCarryVT, Add1_HiNc,  in LowerUDIVREM64()
1665     SDValue Add2_Hi = DAG.getNode(ISD::ADDCARRY, DL, HalfCarryVT, Add2_HiC,  in LowerUDIVREM64()
1669     SDValue Mulhi3 = DAG.getNode(ISD::MULHU, DL, VT, LHS, Add2);  in LowerUDIVREM64()
1671     SDValue Mul3 = DAG.getNode(ISD::MUL, DL, VT, RHS, Mulhi3);  in LowerUDIVREM64()
1673     SDValue Mul3_Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, HalfVT, Mul3, Zero);  in LowerUDIVREM64()
1674     SDValue Mul3_Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, HalfVT, Mul3, One);  in LowerUDIVREM64()
1675     SDValue Sub1_Lo = DAG.getNode(ISD::SUBCARRY, DL, HalfCarryVT, LHS_Lo,  in LowerUDIVREM64()
1677     SDValue Sub1_Hi = DAG.getNode(ISD::SUBCARRY, DL, HalfCarryVT, LHS_Hi,  in LowerUDIVREM64()
1679     SDValue Sub1_Mi = DAG.getNode(ISD::SUB, DL, HalfVT, LHS_Hi, Mul3_Hi);  in LowerUDIVREM64()
1695     SDValue Sub2_Lo = DAG.getNode(ISD::SUBCARRY, DL, HalfCarryVT, Sub1_Lo,  in LowerUDIVREM64()
1697     SDValue Sub2_Mi = DAG.getNode(ISD::SUBCARRY, DL, HalfCarryVT, Sub1_Mi,  in LowerUDIVREM64()
1699     SDValue Sub2_Hi = DAG.getNode(ISD::SUBCARRY, DL, HalfCarryVT, Sub2_Mi,  in LowerUDIVREM64()
1704     SDValue Add3 = DAG.getNode(ISD::ADD, DL, VT, Mulhi3, One64);  in LowerUDIVREM64()
1713     SDValue Add4 = DAG.getNode(ISD::ADD, DL, VT, Add3, One64);  in LowerUDIVREM64()
1715     SDValue Sub3_Lo = DAG.getNode(ISD::SUBCARRY, DL, HalfCarryVT, Sub2_Lo,  in LowerUDIVREM64()
1717     SDValue Sub3_Mi = DAG.getNode(ISD::SUBCARRY, DL, HalfCarryVT, Sub2_Mi,  in LowerUDIVREM64()
1719     SDValue Sub3_Hi = DAG.getNode(ISD::SUBCARRY, DL, HalfCarryVT, Sub3_Mi,  in LowerUDIVREM64()
1741   SDValue DIV_Part = DAG.getNode(ISD::UDIV, DL, HalfVT, LHS_Hi, RHS_Lo);  in LowerUDIVREM64()
1742   SDValue REM_Part = DAG.getNode(ISD::UREM, DL, HalfVT, LHS_Hi, RHS_Lo);  in LowerUDIVREM64()
1746   REM = DAG.getNode(ISD::BITCAST, DL, MVT::i64, REM);  in LowerUDIVREM64()
1757     SDValue HBit = DAG.getNode(ISD::SRL, DL, HalfVT, LHS_Lo, POS);  in LowerUDIVREM64()
1758     HBit = DAG.getNode(ISD::AND, DL, HalfVT, HBit, One);  in LowerUDIVREM64()
1759     HBit = DAG.getNode(ISD::ZERO_EXTEND, DL, VT, HBit);  in LowerUDIVREM64()
1762     REM = DAG.getNode(ISD::SHL, DL, VT, REM, DAG.getConstant(1, DL, VT));  in LowerUDIVREM64()
1764     REM = DAG.getNode(ISD::OR, DL, VT, REM, HBit);  in LowerUDIVREM64()
1769     DIV_Lo = DAG.getNode(ISD::OR, DL, HalfVT, DIV_Lo, realBIT);  in LowerUDIVREM64()
1772     SDValue REM_sub = DAG.getNode(ISD::SUB, DL, VT, REM, RHS);  in LowerUDIVREM64()
1777   DIV = DAG.getNode(ISD::BITCAST, DL, MVT::i64, DIV);  in LowerUDIVREM64()
1803   SDValue RCP = DAG.getNode(AMDGPUISD::URECIP, DL, VT, Den);  in LowerUDIVREM()
1806   SDValue RCP_LO = DAG.getNode(ISD::MUL, DL, VT, RCP, Den);  in LowerUDIVREM()
1809   SDValue RCP_HI = DAG.getNode(ISD::MULHU, DL, VT, RCP, Den);  in LowerUDIVREM()
1812   SDValue NEG_RCP_LO = DAG.getNode(ISD::SUB, DL, VT, DAG.getConstant(0, DL, VT),  in LowerUDIVREM()
1821   SDValue E = DAG.getNode(ISD::MULHU, DL, VT, ABS_RCP_LO, RCP);  in LowerUDIVREM()
1824   SDValue RCP_A_E = DAG.getNode(ISD::ADD, DL, VT, RCP, E);  in LowerUDIVREM()
1827   SDValue RCP_S_E = DAG.getNode(ISD::SUB, DL, VT, RCP, E);  in LowerUDIVREM()
1834   SDValue Quotient = DAG.getNode(ISD::MULHU, DL, VT, Tmp0, Num);  in LowerUDIVREM()
1837   SDValue Num_S_Remainder = DAG.getNode(ISD::MUL, DL, VT, Quotient, Den);  in LowerUDIVREM()
1840   SDValue Remainder = DAG.getNode(ISD::SUB, DL, VT, Num, Num_S_Remainder);  in LowerUDIVREM()
1854   SDValue Tmp1 = DAG.getNode(ISD::AND, DL, VT, Remainder_GE_Den,  in LowerUDIVREM()
1860   SDValue Quotient_A_One = DAG.getNode(ISD::ADD, DL, VT, Quotient,  in LowerUDIVREM()
1864   SDValue Quotient_S_One = DAG.getNode(ISD::SUB, DL, VT, Quotient,  in LowerUDIVREM()
1878   SDValue Remainder_S_Den = DAG.getNode(ISD::SUB, DL, VT, Remainder, Den);  in LowerUDIVREM()
1881   SDValue Remainder_A_Den = DAG.getNode(ISD::ADD, DL, VT, Remainder, Den);  in LowerUDIVREM()
1919     SDValue LHS_Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, HalfVT, LHS, Zero);  in LowerSDIVREM()
1920     SDValue RHS_Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, HalfVT, RHS, Zero);  in LowerSDIVREM()
1921     SDValue DIVREM = DAG.getNode(ISD::SDIVREM, DL, DAG.getVTList(HalfVT, HalfVT),  in LowerSDIVREM()
1924       DAG.getNode(ISD::SIGN_EXTEND, DL, VT, DIVREM.getValue(0)),  in LowerSDIVREM()
1925       DAG.getNode(ISD::SIGN_EXTEND, DL, VT, DIVREM.getValue(1))  in LowerSDIVREM()
1932   SDValue DSign = DAG.getNode(ISD::XOR, DL, VT, LHSign, RHSign);  in LowerSDIVREM()
1935   LHS = DAG.getNode(ISD::ADD, DL, VT, LHS, LHSign);  in LowerSDIVREM()
1936   RHS = DAG.getNode(ISD::ADD, DL, VT, RHS, RHSign);  in LowerSDIVREM()
1938   LHS = DAG.getNode(ISD::XOR, DL, VT, LHS, LHSign);  in LowerSDIVREM()
1939   RHS = DAG.getNode(ISD::XOR, DL, VT, RHS, RHSign);  in LowerSDIVREM()
1941   SDValue Div = DAG.getNode(ISD::UDIVREM, DL, DAG.getVTList(VT, VT), LHS, RHS);  in LowerSDIVREM()
1944   Div = DAG.getNode(ISD::XOR, DL, VT, Div, DSign);  in LowerSDIVREM()
1945   Rem = DAG.getNode(ISD::XOR, DL, VT, Rem, RSign);  in LowerSDIVREM()
1947   Div = DAG.getNode(ISD::SUB, DL, VT, Div, DSign);  in LowerSDIVREM()
1948   Rem = DAG.getNode(ISD::SUB, DL, VT, Rem, RSign);  in LowerSDIVREM()
1966   SDValue Div = DAG.getNode(ISD::FDIV, SL, VT, X, Y);  in LowerFREM()
1967   SDValue Floor = DAG.getNode(ISD::FTRUNC, SL, VT, Div);  in LowerFREM()
1968   SDValue Mul = DAG.getNode(ISD::FMUL, SL, VT, Floor, Y);  in LowerFREM()
1970   return DAG.getNode(ISD::FSUB, SL, VT, X, Mul);  in LowerFREM()
1981   SDValue Trunc = DAG.getNode(ISD::FTRUNC, SL, MVT::f64, Src);  in LowerFCEIL()
1991   SDValue And = DAG.getNode(ISD::AND, SL, SetCCVT, Lt0, NeTrunc);  in LowerFCEIL()
1993   SDValue Add = DAG.getNode(ISD::SELECT, SL, MVT::f64, And, One, Zero);  in LowerFCEIL()
1995   return DAG.getNode(ISD::FADD, SL, MVT::f64, Trunc, Add);  in LowerFCEIL()
2003   SDValue ExpPart = DAG.getNode(AMDGPUISD::BFE_U32, SL, MVT::i32,  in extractF64Exponent()
2007   SDValue Exp = DAG.getNode(ISD::SUB, SL, MVT::i32, ExpPart,  in extractF64Exponent()
2022   SDValue VecSrc = DAG.getNode(ISD::BITCAST, SL, MVT::v2i32, Src);  in LowerFTRUNC()
2026   SDValue Hi = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, SL, MVT::i32, VecSrc, One);  in LowerFTRUNC()
2034   SDValue SignBit = DAG.getNode(ISD::AND, SL, MVT::i32, Hi, SignBitMask);  in LowerFTRUNC()
2038   SignBit64 = DAG.getNode(ISD::BITCAST, SL, MVT::i64, SignBit64);  in LowerFTRUNC()
2040   SDValue BcInt = DAG.getNode(ISD::BITCAST, SL, MVT::i64, Src);  in LowerFTRUNC()
2044   SDValue Shr = DAG.getNode(ISD::SRA, SL, MVT::i64, FractMask, Exp);  in LowerFTRUNC()
2046   SDValue Tmp0 = DAG.getNode(ISD::AND, SL, MVT::i64, BcInt, Not);  in LowerFTRUNC()
2056   SDValue Tmp1 = DAG.getNode(ISD::SELECT, SL, MVT::i64, ExpLt0, SignBit64, Tmp0);  in LowerFTRUNC()
2057   SDValue Tmp2 = DAG.getNode(ISD::SELECT, SL, MVT::i64, ExpGt51, BcInt, Tmp1);  in LowerFTRUNC()
2059   return DAG.getNode(ISD::BITCAST, SL, MVT::f64, Tmp2);  in LowerFTRUNC()
2070   SDValue CopySign = DAG.getNode(ISD::FCOPYSIGN, SL, MVT::f64, C1, Src);  in LowerFRINT()
2074   SDValue Tmp1 = DAG.getNode(ISD::FADD, SL, MVT::f64, Src, CopySign);  in LowerFRINT()
2075   SDValue Tmp2 = DAG.getNode(ISD::FSUB, SL, MVT::f64, Tmp1, CopySign);  in LowerFRINT()
2077   SDValue Fabs = DAG.getNode(ISD::FABS, SL, MVT::f64, Src);  in LowerFRINT()
2093   return DAG.getNode(ISD::FRINT, SDLoc(Op), Op.getValueType(), Op.getOperand(0));  in LowerFNEARBYINT()
2106   SDValue T = DAG.getNode(ISD::FTRUNC, SL, VT, X);  in LowerFROUND32_16()
2110   SDValue Diff = DAG.getNode(ISD::FSUB, SL, VT, X, T);  in LowerFROUND32_16()
2112   SDValue AbsDiff = DAG.getNode(ISD::FABS, SL, VT, Diff);  in LowerFROUND32_16()
2118   SDValue SignOne = DAG.getNode(ISD::FCOPYSIGN, SL, VT, One, X);  in LowerFROUND32_16()
2125   SDValue Sel = DAG.getNode(ISD::SELECT, SL, VT, Cmp, SignOne, Zero);  in LowerFROUND32_16()
2127   return DAG.getNode(ISD::FADD, SL, VT, T, Sel);  in LowerFROUND32_16()
2134   SDValue L = DAG.getNode(ISD::BITCAST, SL, MVT::i64, X);  in LowerFROUND64()
2143   SDValue BC = DAG.getNode(ISD::BITCAST, SL, MVT::v2i32, X);  in LowerFROUND64()
2145   SDValue Hi = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, SL, MVT::i32, BC, One);  in LowerFROUND64()
2152   SDValue M = DAG.getNode(ISD::SRA, SL, MVT::i64, Mask, Exp);  in LowerFROUND64()
2153   SDValue D = DAG.getNode(ISD::SRA, SL, MVT::i64,  in LowerFROUND64()
2158   SDValue Tmp0 = DAG.getNode(ISD::AND, SL, MVT::i64, L, M);  in LowerFROUND64()
2163   SDValue Tmp2 = DAG.getNode(ISD::SELECT, SL, MVT::i64, Tmp1,  in LowerFROUND64()
2165   SDValue K = DAG.getNode(ISD::ADD, SL, MVT::i64, L, Tmp2);  in LowerFROUND64()
2167   K = DAG.getNode(ISD::AND, SL, MVT::i64, K, DAG.getNOT(SL, M, MVT::i64));  in LowerFROUND64()
2168   K = DAG.getNode(ISD::BITCAST, SL, MVT::f64, K);  in LowerFROUND64()
2174   SDValue Mag = DAG.getNode(ISD::SELECT, SL, MVT::f64,  in LowerFROUND64()
2179   SDValue S = DAG.getNode(ISD::FCOPYSIGN, SL, MVT::f64, Mag, X);  in LowerFROUND64()
2181   K = DAG.getNode(ISD::SELECT, SL, MVT::f64, ExpLt0, S, K);  in LowerFROUND64()
2182   K = DAG.getNode(ISD::SELECT, SL, MVT::f64, ExpGt51, X, K);  in LowerFROUND64()
2207   SDValue Trunc = DAG.getNode(ISD::FTRUNC, SL, MVT::f64, Src);  in LowerFFLOOR()
2217   SDValue And = DAG.getNode(ISD::AND, SL, SetCCVT, Lt0, NeTrunc);  in LowerFFLOOR()
2219   SDValue Add = DAG.getNode(ISD::SELECT, SL, MVT::f64, And, NegOne, Zero);  in LowerFFLOOR()
2221   return DAG.getNode(ISD::FADD, SL, MVT::f64, Trunc, Add);  in LowerFFLOOR()
2230   SDValue Log2Operand = DAG.getNode(ISD::FLOG2, SL, VT, Operand);  in LowerFLOG()
2233   return DAG.getNode(ISD::FMUL, SL, VT, Log2Operand, Log2BaseInvertedOperand);  in LowerFLOG()
2260   SDValue Mul = DAG.getNode(ISD::FMUL, SL, VT, Src, K, Op->getFlags());  in lowerFEXP()
2261   return DAG.getNode(ISD::FEXP2, SL, VT, Mul, Op->getFlags());  in lowerFEXP()
2290     return DAG.getNode(NewOpc, SL, MVT::i32, Src);  in LowerCTLZ_CTTZ()
2292   SDValue Vec = DAG.getNode(ISD::BITCAST, SL, MVT::v2i32, Src);  in LowerCTLZ_CTTZ()
2297   SDValue Lo = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, SL, MVT::i32, Vec, Zero);  in LowerCTLZ_CTTZ()
2298   SDValue Hi = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, SL, MVT::i32, Vec, One);  in LowerCTLZ_CTTZ()
2306   SDValue OprLo = DAG.getNode(ISDOpc, SL, MVT::i32, Lo);  in LowerCTLZ_CTTZ()
2307   SDValue OprHi = DAG.getNode(ISDOpc, SL, MVT::i32, Hi);  in LowerCTLZ_CTTZ()
2312     Add = DAG.getNode(ISD::ADD, SL, MVT::i32, OprLo, Bits32);  in LowerCTLZ_CTTZ()
2314     NewOpr = DAG.getNode(ISD::SELECT, SL, MVT::i32, Hi0orLo0, Add, OprHi);  in LowerCTLZ_CTTZ()
2316     Add = DAG.getNode(ISD::ADD, SL, MVT::i32, OprHi, Bits32);  in LowerCTLZ_CTTZ()
2318     NewOpr = DAG.getNode(ISD::SELECT, SL, MVT::i32, Hi0orLo0, Add, OprLo);  in LowerCTLZ_CTTZ()
2328     SDValue SrcIsZero = DAG.getNode(ISD::AND, SL, SetCCVT, Lo0OrHi0, Hi0orLo0);  in LowerCTLZ_CTTZ()
2339     NewOpr = DAG.getNode(ISD::SELECT, SL, MVT::i32,  in LowerCTLZ_CTTZ()
2343   return DAG.getNode(ISD::ZERO_EXTEND, SL, MVT::i64, NewOpr);  in LowerCTLZ_CTTZ()
2374     S = DAG.getNode(ISD::SRA, SL, MVT::i64, L, SignBit);  in LowerINT_TO_FP32()
2376     SDValue LPlusS = DAG.getNode(ISD::ADD, SL, MVT::i64, L, S);  in LowerINT_TO_FP32()
2377     L = DAG.getNode(ISD::XOR, SL, MVT::i64, LPlusS, S);  in LowerINT_TO_FP32()
2386   SDValue LZ = DAG.getNode(ISD::CTLZ_ZERO_UNDEF, SL, MVT::i64, L);  in LowerINT_TO_FP32()
2387   LZ = DAG.getNode(ISD::TRUNCATE, SL, MVT::i32, LZ);  in LowerINT_TO_FP32()
2392     DAG.getNode(ISD::SUB, SL, MVT::i32, K, LZ),  in LowerINT_TO_FP32()
2395   SDValue U = DAG.getNode(ISD::AND, SL, MVT::i64,  in LowerINT_TO_FP32()
2396     DAG.getNode(ISD::SHL, SL, MVT::i64, L, LZ),  in LowerINT_TO_FP32()
2399   SDValue T = DAG.getNode(ISD::AND, SL, MVT::i64, U,  in LowerINT_TO_FP32()
2402   SDValue UShl = DAG.getNode(ISD::SRL, SL, MVT::i64,  in LowerINT_TO_FP32()
2405   SDValue V = DAG.getNode(ISD::OR, SL, MVT::i32,  in LowerINT_TO_FP32()
2406     DAG.getNode(ISD::SHL, SL, MVT::i32, E, DAG.getConstant(23, SL, MVT::i32)),  in LowerINT_TO_FP32()
2407     DAG.getNode(ISD::TRUNCATE, SL, MVT::i32,  UShl));  in LowerINT_TO_FP32()
2415   SDValue VTrunc1 = DAG.getNode(ISD::AND, SL, MVT::i32, V, One);  in LowerINT_TO_FP32()
2421   R = DAG.getNode(ISD::ADD, SL, MVT::i32, V, R);  in LowerINT_TO_FP32()
2422   R = DAG.getNode(ISD::BITCAST, SL, MVT::f32, R);  in LowerINT_TO_FP32()
2427   SDValue RNeg = DAG.getNode(ISD::FNEG, SL, MVT::f32, R);  in LowerINT_TO_FP32()
2436   SDValue BC = DAG.getNode(ISD::BITCAST, SL, MVT::v2i32, Src);  in LowerINT_TO_FP64()
2438   SDValue Lo = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, SL, MVT::i32, BC,  in LowerINT_TO_FP64()
2440   SDValue Hi = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, SL, MVT::i32, BC,  in LowerINT_TO_FP64()
2443   SDValue CvtHi = DAG.getNode(Signed ? ISD::SINT_TO_FP : ISD::UINT_TO_FP,  in LowerINT_TO_FP64()
2446   SDValue CvtLo = DAG.getNode(ISD::UINT_TO_FP, SL, MVT::f64, Lo);  in LowerINT_TO_FP64()
2448   SDValue LdExp = DAG.getNode(AMDGPUISD::LDEXP, SL, MVT::f64, CvtHi,  in LowerINT_TO_FP64()
2451   return DAG.getNode(ISD::FADD, SL, MVT::f64, LdExp, CvtLo);  in LowerINT_TO_FP64()
2466     SDValue IntToFp32 = DAG.getNode(Op.getOpcode(), DL, MVT::f32, Src);  in LowerUINT_TO_FP()
2469         DAG.getNode(ISD::FP_ROUND, DL, MVT::f16, IntToFp32, FPRoundFlag);  in LowerUINT_TO_FP()
2493     SDValue IntToFp32 = DAG.getNode(Op.getOpcode(), DL, MVT::f32, Src);  in LowerSINT_TO_FP()
2496         DAG.getNode(ISD::FP_ROUND, DL, MVT::f16, IntToFp32, FPRoundFlag);  in LowerSINT_TO_FP()
2514   SDValue Trunc = DAG.getNode(ISD::FTRUNC, SL, MVT::f64, Src);  in LowerFP64_TO_INT()
2521   SDValue Mul = DAG.getNode(ISD::FMUL, SL, MVT::f64, Trunc, K0);  in LowerFP64_TO_INT()
2523   SDValue FloorMul = DAG.getNode(ISD::FFLOOR, SL, MVT::f64, Mul);  in LowerFP64_TO_INT()
2526   SDValue Fma = DAG.getNode(ISD::FMA, SL, MVT::f64, FloorMul, K1, Trunc);  in LowerFP64_TO_INT()
2528   SDValue Hi = DAG.getNode(Signed ? ISD::FP_TO_SINT : ISD::FP_TO_UINT, SL,  in LowerFP64_TO_INT()
2530   SDValue Lo = DAG.getNode(ISD::FP_TO_UINT, SL, MVT::i32, Fma);  in LowerFP64_TO_INT()
2534   return DAG.getNode(ISD::BITCAST, SL, MVT::i64, Result);  in LowerFP64_TO_INT()
2543     return DAG.getNode(AMDGPUISD::FP_TO_FP16, DL, Op.getValueType(), N0);  in LowerFP_TO_FP16()
2558   SDValue U = DAG.getNode(ISD::BITCAST, DL, MVT::i64, N0);  in LowerFP_TO_FP16()
2559   SDValue UH = DAG.getNode(ISD::SRL, DL, MVT::i64, U,  in LowerFP_TO_FP16()
2563   SDValue E = DAG.getNode(ISD::SRL, DL, MVT::i32, UH,  in LowerFP_TO_FP16()
2565   E = DAG.getNode(ISD::AND, DL, MVT::i32, E,  in LowerFP_TO_FP16()
2569   E = DAG.getNode(ISD::ADD, DL, MVT::i32, E,  in LowerFP_TO_FP16()
2572   SDValue M = DAG.getNode(ISD::SRL, DL, MVT::i32, UH,  in LowerFP_TO_FP16()
2574   M = DAG.getNode(ISD::AND, DL, MVT::i32, M,  in LowerFP_TO_FP16()
2577   SDValue MaskedSig = DAG.getNode(ISD::AND, DL, MVT::i32, UH,  in LowerFP_TO_FP16()
2579   MaskedSig = DAG.getNode(ISD::OR, DL, MVT::i32, MaskedSig, U);  in LowerFP_TO_FP16()
2582   M = DAG.getNode(ISD::OR, DL, MVT::i32, M, Lo40Set);  in LowerFP_TO_FP16()
2585   SDValue I = DAG.getNode(ISD::OR, DL, MVT::i32,  in LowerFP_TO_FP16()
2590   SDValue N = DAG.getNode(ISD::OR, DL, MVT::i32, M,  in LowerFP_TO_FP16()
2591       DAG.getNode(ISD::SHL, DL, MVT::i32, E,  in LowerFP_TO_FP16()
2595   SDValue OneSubExp = DAG.getNode(ISD::SUB, DL, MVT::i32,  in LowerFP_TO_FP16()
2597   SDValue B = DAG.getNode(ISD::SMAX, DL, MVT::i32, OneSubExp, Zero);  in LowerFP_TO_FP16()
2598   B = DAG.getNode(ISD::SMIN, DL, MVT::i32, B,  in LowerFP_TO_FP16()
2601   SDValue SigSetHigh = DAG.getNode(ISD::OR, DL, MVT::i32, M,  in LowerFP_TO_FP16()
2604   SDValue D = DAG.getNode(ISD::SRL, DL, MVT::i32, SigSetHigh, B);  in LowerFP_TO_FP16()
2605   SDValue D0 = DAG.getNode(ISD::SHL, DL, MVT::i32, D, B);  in LowerFP_TO_FP16()
2607   D = DAG.getNode(ISD::OR, DL, MVT::i32, D, D1);  in LowerFP_TO_FP16()
2610   SDValue VLow3 = DAG.getNode(ISD::AND, DL, MVT::i32, V,  in LowerFP_TO_FP16()
2612   V = DAG.getNode(ISD::SRL, DL, MVT::i32, V,  in LowerFP_TO_FP16()
2618   V1 = DAG.getNode(ISD::OR, DL, MVT::i32, V0, V1);  in LowerFP_TO_FP16()
2619   V = DAG.getNode(ISD::ADD, DL, MVT::i32, V, V1);  in LowerFP_TO_FP16()
2627   SDValue Sign = DAG.getNode(ISD::SRL, DL, MVT::i32, UH,  in LowerFP_TO_FP16()
2629   Sign = DAG.getNode(ISD::AND, DL, MVT::i32, Sign,  in LowerFP_TO_FP16()
2632   V = DAG.getNode(ISD::OR, DL, MVT::i32, Sign, V);  in LowerFP_TO_FP16()
2646     SDValue FPExtend = DAG.getNode(ISD::FP_EXTEND, DL, MVT::f32, Src);  in LowerFP_TO_SINT()
2648         DAG.getNode(Op.getOpcode(), DL, MVT::i64, FPExtend);  in LowerFP_TO_SINT()
2669     SDValue FPExtend = DAG.getNode(ISD::FP_EXTEND, DL, MVT::f32, Src);  in LowerFP_TO_UINT()
2671         DAG.getNode(Op.getOpcode(), DL, MVT::i64, FPExtend);  in LowerFP_TO_UINT()
2700     Args[I] = DAG.getNode(ISD::SIGN_EXTEND_INREG, DL, ScalarVT, Args[I], VTOp);  in LowerSIGN_EXTEND_INREG()
2734     return DAG.getNode(Node24->getOpcode(), SDLoc(Node24), Node24->getVTList(),  in simplifyI24()
2837   SDValue BC = DAG.getNode(ISD::BITCAST, SL, VT, NewLoad);  in performLoadCombine()
2887   SDValue CastVal = DAG.getNode(ISD::BITCAST, SL, NewVT, Val);  in performStoreCombine()
2889     SDValue CastBack = DAG.getNode(ISD::BITCAST, SL, VT, CastVal);  in performStoreCombine()
2915       SDValue NewInReg = DAG.getNode(N->getOpcode(), SL, SrcVT, Src, N1);  in performAssertSZExtCombine()
2916       return DAG.getNode(ISD::TRUNCATE, SL, N->getValueType(0), NewInReg);  in performAssertSZExtCombine()
2935   SDValue LoAnd = DAG.getNode(Opc, SL, MVT::i32, Lo, LoRHS);  in splitBinaryBitConstantOpImpl()
2936   SDValue HiAnd = DAG.getNode(Opc, SL, MVT::i32, Hi, HiRHS);  in splitBinaryBitConstantOpImpl()
2940   DCI.AddToWorklist(Lo.getNode());  in splitBinaryBitConstantOpImpl()
2941   DCI.AddToWorklist(Hi.getNode());  in splitBinaryBitConstantOpImpl()
2944   return DAG.getNode(ISD::BITCAST, SL, MVT::i64, Vec);  in splitBinaryBitConstantOpImpl()
2977       return DAG.getNode(ISD::BITCAST, SL, MVT::i32, Vec);  in performShlCombine()
2988     SDValue Shl = DAG.getNode(ISD::SHL, SL, XVT, X, SDValue(RHS, 0));  in performShlCombine()
3006   SDValue Lo = DAG.getNode(ISD::TRUNCATE, SL, MVT::i32, LHS);  in performShlCombine()
3007   SDValue NewShift = DAG.getNode(ISD::SHL, SL, MVT::i32, Lo, ShiftAmt);  in performShlCombine()
3012   return DAG.getNode(ISD::BITCAST, SL, MVT::i64, Vec);  in performShlCombine()
3031     SDValue NewShift = DAG.getNode(ISD::SRA, SL, MVT::i32, Hi,  in performSraCombine()
3035     return DAG.getNode(ISD::BITCAST, SL, MVT::i64, BuildVec);  in performSraCombine()
3041     SDValue NewShift = DAG.getNode(ISD::SRA, SL, MVT::i32, Hi,  in performSraCombine()
3044     return DAG.getNode(ISD::BITCAST, SL, MVT::i64, BuildVec);  in performSraCombine()
3073   SDValue VecOp = DAG.getNode(ISD::BITCAST, SL, MVT::v2i32, N->getOperand(0));  in performSrlCombine()
3074   SDValue Hi = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, SL, MVT::i32,  in performSrlCombine()
3078   SDValue NewShift = DAG.getNode(ISD::SRL, SL, MVT::i32, Hi, NewConst);  in performSrlCombine()
3082   return DAG.getNode(ISD::BITCAST, SL, MVT::i64, BuildPair);  in performSrlCombine()
3100           Elt0 = DAG.getNode(ISD::BITCAST, SL,  in performTruncateCombine()
3104         return DAG.getNode(ISD::TRUNCATE, SL, VT, Elt0);  in performTruncateCombine()
3121             SrcElt = DAG.getNode(ISD::BITCAST, SL,  in performTruncateCombine()
3125           return DAG.getNode(ISD::TRUNCATE, SL, VT, SrcElt);  in performTruncateCombine()
3151         SDValue Trunc = DAG.getNode(ISD::TRUNCATE, SL, MidVT,  in performTruncateCombine()
3153         DCI.AddToWorklist(Trunc.getNode());  in performTruncateCombine()
3157           DCI.AddToWorklist(Amt.getNode());  in performTruncateCombine()
3160         SDValue ShrunkShift = DAG.getNode(Src.getOpcode(), SL, MidVT,  in performTruncateCombine()
3162         return DAG.getNode(ISD::TRUNCATE, SL, VT, ShrunkShift);  in performTruncateCombine()
3178     return DAG.getNode(MulOpc, SL, MVT::i32, N0, N1);  in getMul24()
3187   SDValue Mul = DAG.getNode(MulOpc, SL,  in getMul24()
3190   return DAG.getNode(ISD::BUILD_PAIR, SL, MVT::i64,  in getMul24()
3260   SDValue Mulhi = DAG.getNode(AMDGPUISD::MULHI_I24, DL, MVT::i32, N0, N1);  in performMulhsCombine()
3261   DCI.AddToWorklist(Mulhi.getNode());  in performMulhsCombine()
3284   SDValue Mulhi = DAG.getNode(AMDGPUISD::MULHI_U24, DL, MVT::i32, N0, N1);  in performMulhuCombine()
3285   DCI.AddToWorklist(Mulhi.getNode());  in performMulhuCombine()
3307   SDValue MulLo = DAG.getNode(MulLoOpc, SL, MVT::i32, N0, N1);  in performMulLoHi24Combine()
3308   SDValue MulHi = DAG.getNode(MulHiOpc, SL, MVT::i32, N0, N1);  in performMulLoHi24Combine()
3329     Op = DAG.getNode(ISD::ZERO_EXTEND, DL, MVT::i32, Op);  in getFFBX_U32()
3331   SDValue FFBX = DAG.getNode(Opc, DL, MVT::i32, Op);  in getFFBX_U32()
3333     FFBX = DAG.getNode(ISD::TRUNCATE, DL, VT, FFBX);  in getFFBX_U32()
3389   SDValue NewSelect = DAG.getNode(ISD::SELECT, SL, VT, Cond,  in distributeOpThroughSelect()
3391   DCI.AddToWorklist(NewSelect.getNode());  in distributeOpThroughSelect()
3392   return DAG.getNode(Op, SL, VT, NewSelect);  in distributeOpThroughSelect()
3444         NewRHS = DAG.getNode(ISD::FNEG, SL, VT, RHS);  in foldFreeOpFromSelect()
3451       SDValue NewSelect = DAG.getNode(ISD::SELECT, SL, VT,  in foldFreeOpFromSelect()
3453       DCI.AddToWorklist(NewSelect.getNode());  in foldFreeOpFromSelect()
3454       return DAG.getNode(LHS.getOpcode(), SL, VT, NewSelect);  in foldFreeOpFromSelect()
3494       return DAG.getNode(ISD::SELECT, SL, VT, NewCond, False, True);  in performSelectCombine()
3572         (allUsesHaveSourceMods(N) || !allUsesHaveSourceMods(N0.getNode())))  in performFNegCombine()
3587       LHS = DAG.getNode(ISD::FNEG, SL, VT, LHS);  in performFNegCombine()
3592       RHS = DAG.getNode(ISD::FNEG, SL, VT, RHS);  in performFNegCombine()
3596     SDValue Res = DAG.getNode(ISD::FADD, SL, VT, LHS, RHS, N0->getFlags());  in performFNegCombine()
3598       DAG.ReplaceAllUsesWith(N0, DAG.getNode(ISD::FNEG, SL, VT, Res));  in performFNegCombine()
3613       RHS = DAG.getNode(ISD::FNEG, SL, VT, RHS);  in performFNegCombine()
3615     SDValue Res = DAG.getNode(Opc, SL, VT, LHS, RHS, N0->getFlags());  in performFNegCombine()
3617       DAG.ReplaceAllUsesWith(N0, DAG.getNode(ISD::FNEG, SL, VT, Res));  in performFNegCombine()
3635       MHS = DAG.getNode(ISD::FNEG, SL, VT, MHS);  in performFNegCombine()
3638       RHS = DAG.getNode(ISD::FNEG, SL, VT, RHS);  in performFNegCombine()
3642     SDValue Res = DAG.getNode(Opc, SL, VT, LHS, MHS, RHS);  in performFNegCombine()
3644       DAG.ReplaceAllUsesWith(N0, DAG.getNode(ISD::FNEG, SL, VT, Res));  in performFNegCombine()
3666     SDValue NegLHS = DAG.getNode(ISD::FNEG, SL, VT, LHS);  in performFNegCombine()
3667     SDValue NegRHS = DAG.getNode(ISD::FNEG, SL, VT, RHS);  in performFNegCombine()
3670     SDValue Res = DAG.getNode(Opposite, SL, VT, NegLHS, NegRHS, N0->getFlags());  in performFNegCombine()
3672       DAG.ReplaceAllUsesWith(N0, DAG.getNode(ISD::FNEG, SL, VT, Res));  in performFNegCombine()
3678       Ops[I] = DAG.getNode(ISD::FNEG, SL, VT, N0->getOperand(I), N0->getFlags());  in performFNegCombine()
3680     SDValue Res = DAG.getNode(AMDGPUISD::FMED3, SL, VT, Ops, N0->getFlags());  in performFNegCombine()
3682       DAG.ReplaceAllUsesWith(N0, DAG.getNode(ISD::FNEG, SL, VT, Res));  in performFNegCombine()
3699       return DAG.getNode(Opc, SL, VT, CvtSrc.getOperand(0));  in performFNegCombine()
3707     SDValue Neg = DAG.getNode(ISD::FNEG, SL, CvtSrc.getValueType(), CvtSrc);  in performFNegCombine()
3708     return DAG.getNode(Opc, SL, VT, Neg, N0->getFlags());  in performFNegCombine()
3715       return DAG.getNode(ISD::FP_ROUND, SL, VT,  in performFNegCombine()
3723     SDValue Neg = DAG.getNode(ISD::FNEG, SL, CvtSrc.getValueType(), CvtSrc);  in performFNegCombine()
3724     return DAG.getNode(ISD::FP_ROUND, SL, VT, Neg, N0.getOperand(1));  in performFNegCombine()
3736     SDValue IntFNeg = DAG.getNode(ISD::XOR, SL, SrcVT, Src,  in performFNegCombine()
3738     return DAG.getNode(ISD::FP16_TO_FP, SL, N->getValueType(0), IntFNeg);  in performFNegCombine()
3761     SDValue IntFAbs = DAG.getNode(ISD::AND, SL, SrcVT, Src,  in performFAbsCombine()
3763     return DAG.getNode(ISD::FP16_TO_FP, SL, N->getValueType(0), IntFAbs);  in performFAbsCombine()
3811             CastedElts.push_back(DAG.getNode(ISD::BITCAST, DL, DestEltVT, Elt));  in PerformDAGCombine()
3831         SDValue BV = DAG.getNode(ISD::BUILD_VECTOR, SL, MVT::v2i32,  in PerformDAGCombine()
3834         return DAG.getNode(ISD::BITCAST, SL, DestVT, BV);  in PerformDAGCombine()
3842       SDValue Vec = DAG.getNode(ISD::BUILD_VECTOR, SL, MVT::v2i32,  in PerformDAGCombine()
3846       return DAG.getNode(ISD::BITCAST, SL, DestVT, Vec);  in PerformDAGCombine()
3931         return DAG.getNode(ISD::SIGN_EXTEND_INREG, DL, MVT::i32, BitsFrom,  in PerformDAGCombine()
3957       return DAG.getNode(Signed ? ISD::SRA : ISD::SRL, DL, MVT::i32,  in PerformDAGCombine()
4235     return DAG.getNode(AMDGPUISD::RSQ, SDLoc(Operand), VT, Operand);  in getSqrtEstimate()
4256     return DAG.getNode(AMDGPUISD::RCP, SDLoc(Operand), VT, Operand);  in getRecipEstimate()