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Searched refs:DestReg (Results 1 – 25 of 94) sorted by relevance

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/freebsd-12.1/contrib/llvm/lib/Target/ARM/
H A DThumb2InstrInfo.cpp127 if (!ARM::GPRRegClass.contains(DestReg, SrcReg)) in copyPhysReg()
130 BuildMI(MBB, I, DL, get(ARM::tMOVr), DestReg) in copyPhysReg()
180 unsigned DestReg, int FI, in loadRegFromStackSlot() argument
206 MRI->constrainRegClass(DestReg, in loadRegFromStackSlot()
239 if (NumBytes == 0 && DestReg != BaseReg) { in emitT2RegPlusImmediate()
251 if (DestReg != ARM::SP && DestReg != BaseReg && in emitT2RegPlusImmediate()
264 .addReg(DestReg) in emitT2RegPlusImmediate()
274 .addReg(DestReg, RegState::Kill) in emitT2RegPlusImmediate()
286 .addReg(DestReg, RegState::Kill) in emitT2RegPlusImmediate()
298 if (DestReg == ARM::SP && BaseReg != ARM::SP) { in emitT2RegPlusImmediate()
[all …]
H A DThumbRegisterInfo.cpp111 assert((isARMLowRegister(DestReg) || isVirtualRegister(DestReg)) && in emitLoadConstPool()
131 bool isHigh = !isARMLowRegister(DestReg) || in emitThumbRegPlusImmInReg()
142 unsigned LdReg = DestReg; in emitThumbRegPlusImmInReg()
143 if (DestReg == ARM::SP) in emitThumbRegPlusImmInReg()
145 if (!isARMLowRegister(DestReg) && !MRI.isVirtualRegister(DestReg)) in emitThumbRegPlusImmInReg()
175 if (DestReg == ARM::SP || isSub) in emitThumbRegPlusImmInReg()
219 if (DestReg == ARM::SP) { in emitThumbRegPlusImmediate()
231 } else if (isARMLowRegister(DestReg)) { in emitThumbRegPlusImmediate()
238 } else if (DestReg == BaseReg) { in emitThumbRegPlusImmediate()
255 if (DestReg == BaseReg) { in emitThumbRegPlusImmediate()
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H A DThumb1InstrInfo.cpp47 assert(ARM::GPRRegClass.contains(DestReg, SrcReg) && in copyPhysReg()
51 || !ARM::tGPRRegClass.contains(DestReg)) in copyPhysReg()
52 BuildMI(MBB, I, DL, get(ARM::tMOVr), DestReg) in copyPhysReg()
62 BuildMI(MBB, I, DL, get(ARM::tMOVSr), DestReg) in copyPhysReg()
74 .addReg(DestReg, getDefRegState(true)); in copyPhysReg()
109 unsigned DestReg, int FI, in loadRegFromStackSlot() argument
113 (TargetRegisterInfo::isPhysicalRegister(DestReg) && in loadRegFromStackSlot()
114 isARMLowRegister(DestReg))) && "Unknown regclass!"); in loadRegFromStackSlot()
117 (TargetRegisterInfo::isPhysicalRegister(DestReg) && in loadRegFromStackSlot()
118 isARMLowRegister(DestReg))) { in loadRegFromStackSlot()
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H A DARMBaseInstrInfo.cpp817 BuildMI(MBB, I, DL, get(ARM::MOVr), DestReg) in copyPhysReg()
901 } else if (DestReg == ARM::CPSR) { in copyPhysReg()
937 Mov->addRegisterDefined(DestReg, TRI); in copyPhysReg()
1191 unsigned DestReg, int FI, in loadRegFromStackSlot() argument
1206 BuildMI(MBB, I, DL, get(ARM::VLDRH), DestReg) in loadRegFromStackSlot()
1222 BuildMI(MBB, I, DL, get(ARM::VLDRS), DestReg) in loadRegFromStackSlot()
1232 BuildMI(MBB, I, DL, get(ARM::VLDRD), DestReg) in loadRegFromStackSlot()
2116 unsigned DestReg = MI.getOperand(0).getReg(); in optimizeSelect() local
2230 if (NumBytes == 0 && DestReg != BaseReg) { in emitARMRegPlusImmediate()
2254 BuildMI(MBB, MBBI, dl, TII.get(Opc), DestReg) in emitARMRegPlusImmediate()
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/freebsd-12.1/contrib/llvm/lib/Target/Sparc/
H A DSparcInstrInfo.cpp322 if (SP::IntRegsRegClass.contains(DestReg, SrcReg)) in copyPhysReg()
331 BuildMI(MBB, I, DL, get(SP::FMOVS), DestReg) in copyPhysReg()
335 BuildMI(MBB, I, DL, get(SP::FMOVD), DestReg) in copyPhysReg()
346 BuildMI(MBB, I, DL, get(SP::FMOVQ), DestReg) in copyPhysReg()
360 } else if (SP::ASRRegsRegClass.contains(DestReg) && in copyPhysReg()
362 BuildMI(MBB, I, DL, get(SP::WRASRrr), DestReg) in copyPhysReg()
365 } else if (SP::IntRegsRegClass.contains(DestReg) && in copyPhysReg()
367 BuildMI(MBB, I, DL, get(SP::RDASR), DestReg) in copyPhysReg()
379 unsigned Dst = TRI->getSubReg(DestReg, subRegIdx[i]); in copyPhysReg()
390 MovMI->addRegisterDefined(DestReg, TRI); in copyPhysReg()
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/freebsd-12.1/contrib/llvm/lib/Target/RISCV/
H A DRISCVExpandPseudoInsts.cpp161 unsigned DestReg = MI.getOperand(0).getReg(); in doAtomicBinOpExpansion() local
180 .addReg(DestReg) in doAtomicBinOpExpansion()
223 unsigned DestReg = MI.getOperand(0).getReg(); in doMaskedAtomicBinOpExpansion() local
251 .addReg(DestReg) in doMaskedAtomicBinOpExpansion()
256 .addReg(DestReg) in doMaskedAtomicBinOpExpansion()
261 .addReg(DestReg) in doMaskedAtomicBinOpExpansion()
362 unsigned DestReg = MI.getOperand(0).getReg(); in expandAtomicMinMaxOp() local
382 .addReg(DestReg) in expandAtomicMinMaxOp()
385 .addReg(DestReg) in expandAtomicMinMaxOp()
491 .addReg(DestReg) in expandAtomicCmpXchg()
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H A DRISCVMergeBaseOffset.cpp182 unsigned DestReg = LoADDI.getOperand(0).getReg(); in detectAndFoldOffset() local
183 assert(MRI->hasOneUse(DestReg) && "expected one use for LoADDI"); in detectAndFoldOffset()
185 MachineInstr &Tail = *MRI->use_begin(DestReg)->getParent(); in detectAndFoldOffset()
208 if (!matchLargeOffset(Tail, DestReg, Offset)) in detectAndFoldOffset()
237 if (DestReg != BaseAddrReg) in detectAndFoldOffset()
/freebsd-12.1/contrib/llvm/lib/Target/Mips/
H A DMipsFastISel.cpp399 return DestReg; in materializeFP()
407 return DestReg; in materializeFP()
423 emitInst(Mips::LW, DestReg) in materializeGV()
430 .addReg(DestReg) in materializeGV()
432 DestReg = TempReg; in materializeGV()
434 return DestReg; in materializeGV()
440 emitInst(Mips::LW, DestReg) in materializeExternalCallSym()
443 return DestReg; in materializeExternalCallSym()
1091 if (!DestReg) in selectFPTrunc()
1599 if (DestReg == 0) in fastLowerIntrinsicCall()
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H A DMipsSEInstrInfo.cpp125 Opc = Mips::MTHI, DestReg = 0; in copyPhysReg()
127 Opc = Mips::MTLO, DestReg = 0; in copyPhysReg()
139 .addReg(DestReg) in copyPhysReg()
162 Opc = Mips::MTHI64, DestReg = 0; in copyPhysReg()
164 Opc = Mips::MTLO64, DestReg = 0; in copyPhysReg()
177 if (DestReg) in copyPhysReg()
178 MIB.addReg(DestReg, RegState::Define); in copyPhysReg()
335 (DestReg == Mips::LO0 || DestReg == Mips::LO0_64 || in loadRegFromStack()
336 DestReg == Mips::HI0 || DestReg == Mips::HI0_64); in loadRegFromStack()
390 if (DestReg == Mips::HI0) in loadRegFromStack()
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H A DMips16InstrInfo.cpp72 const DebugLoc &DL, unsigned DestReg, in copyPhysReg() argument
76 if (Mips::CPU16RegsRegClass.contains(DestReg) && in copyPhysReg()
79 else if (Mips::GPR32RegClass.contains(DestReg) && in copyPhysReg()
83 (Mips::CPU16RegsRegClass.contains(DestReg))) in copyPhysReg()
86 (Mips::CPU16RegsRegClass.contains(DestReg))) in copyPhysReg()
93 if (DestReg) in copyPhysReg()
94 MIB.addReg(DestReg, RegState::Define); in copyPhysReg()
131 unsigned DestReg, int FI, in loadRegFromStack() argument
143 BuildMI(MBB, I, DL, get(Opc), DestReg).addFrameIndex(FI).addImm(Offset) in loadRegFromStack()
/freebsd-12.1/contrib/llvm/lib/Target/AArch64/
H A DAArch64AsmPrinter.cpp538 unsigned DestReg = MI.getOperand(0).getReg(); in LowerJumpTableDestSmall() local
552 .addReg(DestReg) in LowerJumpTableDestSmall()
568 .addReg(DestReg) in LowerJumpTableDestSmall()
569 .addReg(DestReg) in LowerJumpTableDestSmall()
643 unsigned DestReg = MI.getOperand(0).getReg(); in EmitFMov0() local
646 if (AArch64::H0 <= DestReg && DestReg <= AArch64::H31) in EmitFMov0()
647 DestReg = AArch64::Q0 + (DestReg - AArch64::H0); in EmitFMov0()
648 else if (AArch64::S0 <= DestReg && DestReg <= AArch64::S31) in EmitFMov0()
649 DestReg = AArch64::Q0 + (DestReg - AArch64::S0); in EmitFMov0()
651 assert(AArch64::D0 <= DestReg && DestReg <= AArch64::D31); in EmitFMov0()
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H A DAArch64InstrInfo.cpp2499 DestReg = RI.getMatchingSuperReg(DestReg, AArch64::dsub, in copyPhysReg()
2516 DestReg = RI.getMatchingSuperReg(DestReg, AArch64::ssub, in copyPhysReg()
2533 DestReg = RI.getMatchingSuperReg(DestReg, AArch64::hsub, in copyPhysReg()
2541 DestReg = RI.getMatchingSuperReg(DestReg, AArch64::hsub, in copyPhysReg()
2554 DestReg = RI.getMatchingSuperReg(DestReg, AArch64::bsub, in copyPhysReg()
2562 DestReg = RI.getMatchingSuperReg(DestReg, AArch64::bsub, in copyPhysReg()
2599 if (DestReg == AArch64::NZCV) { in copyPhysReg()
2755 unsigned DestReg0 = DestReg; in loadRegPairFromStackSlot()
2756 unsigned DestReg1 = DestReg; in loadRegPairFromStackSlot()
2811 assert(DestReg != AArch64::SP); in loadRegFromStackSlot()
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H A DAArch64A57FPLoadBalancing.cpp615 unsigned DestReg = MI->getOperand(0).getReg(); in scanInstruction() local
618 << printReg(DestReg, TRI) << " at " << *MI); in scanInstruction()
620 auto G = llvm::make_unique<Chain>(MI, Idx, getColor(DestReg)); in scanInstruction()
621 ActiveChains[DestReg] = G.get(); in scanInstruction()
628 unsigned DestReg = MI->getOperand(0).getReg(); in scanInstruction() local
633 if (DestReg != AccumReg) in scanInstruction()
648 ActiveChains[AccumReg]->add(MI, Idx, getColor(DestReg)); in scanInstruction()
650 if (DestReg != AccumReg) { in scanInstruction()
651 ActiveChains[DestReg] = ActiveChains[AccumReg]; in scanInstruction()
664 << printReg(DestReg, TRI) << "\n"); in scanInstruction()
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/freebsd-12.1/contrib/llvm/lib/Target/AMDGPU/
H A DR600MachineScheduler.cpp274 unsigned DestReg = MI->getOperand(0).getReg(); in getAluKind() local
275 if (regBelongsToClass(DestReg, &R600::R600_TReg32_XRegClass) || in getAluKind()
276 regBelongsToClass(DestReg, &R600::R600_AddrRegClass)) in getAluKind()
278 if (regBelongsToClass(DestReg, &R600::R600_TReg32_YRegClass)) in getAluKind()
280 if (regBelongsToClass(DestReg, &R600::R600_TReg32_ZRegClass)) in getAluKind()
282 if (regBelongsToClass(DestReg, &R600::R600_TReg32_WRegClass)) in getAluKind()
284 if (regBelongsToClass(DestReg, &R600::R600_Reg128RegClass)) in getAluKind()
361 unsigned DestReg = MI->getOperand(DstIndex).getReg(); in AssignSlot() local
368 MO.getReg() == DestReg) in AssignSlot()
374 MRI->constrainRegClass(DestReg, &R600::R600_TReg32_XRegClass); in AssignSlot()
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H A DAMDGPUMachineCFGStructurizer.cpp62 unsigned DestReg;
86 void deleteDef(unsigned DestReg);
92 unsigned &DestReg);
131 return Info->DestReg; in phiInfoElementGetDest()
136 Info->DestReg = NewDef; in phiInfoElementSetDef()
219 NewElement->DestReg = DestReg; in addDest()
257 unsigned DestReg; in isSource() local
2082 unsigned DestReg; in rewriteLiveOutRegs() local
2100 unsigned DestReg = *DRI; in prunePHIInfo() local
2219 unsigned DestReg = *DRI; in createEntryPHIs() local
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/freebsd-12.1/contrib/llvm/lib/Target/Hexagon/
H A DHexagonSplitConst32AndConst64.cpp80 unsigned DestReg = MI.getOperand(0).getReg(); in runOnMachineFunction() local
83 BuildMI(B, MI, DL, TII->get(Hexagon::A2_tfrsi), DestReg) in runOnMachineFunction()
87 unsigned DestReg = MI.getOperand(0).getReg(); in runOnMachineFunction() local
90 unsigned DestLo = TRI->getSubReg(DestReg, Hexagon::isub_lo); in runOnMachineFunction()
91 unsigned DestHi = TRI->getSubReg(DestReg, Hexagon::isub_hi); in runOnMachineFunction()
H A DHexagonCopyToCombine.cpp105 void emitCombineRR(MachineBasicBlock::iterator &Before, unsigned DestReg,
108 void emitCombineRI(MachineBasicBlock::iterator &Before, unsigned DestReg,
111 void emitCombineIR(MachineBasicBlock::iterator &Before, unsigned DestReg,
114 void emitCombineII(MachineBasicBlock::iterator &Before, unsigned DestReg,
117 void emitConst64(MachineBasicBlock::iterator &Before, unsigned DestReg,
137 unsigned DestReg = Op0.getReg(); in isCombinableInstType() local
139 return Hexagon::IntRegsRegClass.contains(DestReg) && in isCombinableInstType()
150 unsigned DestReg = Op0.getReg(); in isCombinableInstType() local
159 return Hexagon::IntRegsRegClass.contains(DestReg) && in isCombinableInstType()
250 unsigned DestReg, in isUnsafeToMoveAcross() argument
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/freebsd-12.1/contrib/llvm/lib/Target/SystemZ/
H A DSystemZInstrInfo.cpp165 unsigned DestReg = MI.getOperand(0).getReg(); in expandRIEPseudo() local
167 bool DestIsHigh = isHighReg(DestReg); in expandRIEPseudo()
176 MI.getOperand(1).setReg(DestReg); in expandRIEPseudo()
207 unsigned DestReg = MI.getOperand(0).getReg(); in expandLOCRPseudo() local
209 bool DestIsHigh = isHighReg(DestReg); in expandLOCRPseudo()
284 bool DestIsHigh = isHighReg(DestReg); in emitGRX32Move()
297 return BuildMI(MBB, MBBI, DL, get(Opcode), DestReg) in emitGRX32Move()
298 .addReg(DestReg, RegState::Undef) in emitGRX32Move()
845 if (DestReg == SystemZ::CC) { in copyPhysReg()
880 BuildMI(MBB, MBBI, DL, get(Opcode), DestReg) in copyPhysReg()
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/freebsd-12.1/contrib/llvm/include/llvm/CodeGen/
H A DMachineInstrBuilder.h312 const MCInstrDesc &MCID, unsigned DestReg) { in BuildMI() argument
314 .addReg(DestReg, RegState::Define); in BuildMI()
323 unsigned DestReg) { in BuildMI() argument
327 return MachineInstrBuilder(MF, MI).addReg(DestReg, RegState::Define); in BuildMI()
339 unsigned DestReg) { in BuildMI() argument
343 return MachineInstrBuilder(MF, MI).addReg(DestReg, RegState::Define); in BuildMI()
348 unsigned DestReg) { in BuildMI() argument
353 return BuildMI(BB, MachineBasicBlock::iterator(I), DL, MCID, DestReg); in BuildMI()
358 unsigned DestReg) { in BuildMI() argument
359 return BuildMI(BB, *I, DL, MCID, DestReg); in BuildMI()
[all …]
/freebsd-12.1/contrib/llvm/lib/Target/BPF/
H A DBPFInstrInfo.cpp34 const DebugLoc &DL, unsigned DestReg, in copyPhysReg() argument
36 if (BPF::GPRRegClass.contains(DestReg, SrcReg)) in copyPhysReg()
37 BuildMI(MBB, I, DL, get(BPF::MOV_rr), DestReg) in copyPhysReg()
39 else if (BPF::GPR32RegClass.contains(DestReg, SrcReg)) in copyPhysReg()
40 BuildMI(MBB, I, DL, get(BPF::MOV_rr_32), DestReg) in copyPhysReg()
150 unsigned DestReg, int FI, in loadRegFromStackSlot() argument
158 BuildMI(MBB, I, DL, get(BPF::LDD), DestReg).addFrameIndex(FI).addImm(0); in loadRegFromStackSlot()
160 BuildMI(MBB, I, DL, get(BPF::LDW32), DestReg).addFrameIndex(FI).addImm(0); in loadRegFromStackSlot()
/freebsd-12.1/contrib/llvm/lib/Target/MSP430/
H A DMSP430InstrInfo.cpp66 unsigned DestReg, int FrameIdx, in loadRegFromStackSlot() argument
81 .addReg(DestReg, getDefRegState(true)).addFrameIndex(FrameIdx) in loadRegFromStackSlot()
85 .addReg(DestReg, getDefRegState(true)).addFrameIndex(FrameIdx) in loadRegFromStackSlot()
93 const DebugLoc &DL, unsigned DestReg, in copyPhysReg() argument
96 if (MSP430::GR16RegClass.contains(DestReg, SrcReg)) in copyPhysReg()
98 else if (MSP430::GR8RegClass.contains(DestReg, SrcReg)) in copyPhysReg()
103 BuildMI(MBB, I, DL, get(Opc), DestReg) in copyPhysReg()
/freebsd-12.1/contrib/llvm/lib/Target/WebAssembly/
H A DWebAssemblyInstrInfo.cpp54 const DebugLoc &DL, unsigned DestReg, in copyPhysReg() argument
60 TargetRegisterInfo::isVirtualRegister(DestReg) in copyPhysReg()
61 ? MRI.getRegClass(DestReg) in copyPhysReg()
62 : MRI.getTargetRegisterInfo()->getMinimalPhysRegClass(DestReg); in copyPhysReg()
78 BuildMI(MBB, I, DL, get(CopyOpcode), DestReg) in copyPhysReg()
/freebsd-12.1/contrib/llvm/lib/Target/AVR/
H A DAVRInstrInfo.cpp44 const DebugLoc &DL, unsigned DestReg, in copyPhysReg() argument
51 if (AVR::DREGSRegClass.contains(DestReg, SrcReg)) { in copyPhysReg()
53 BuildMI(MBB, MI, DL, get(AVR::MOVWRdRr), DestReg) in copyPhysReg()
58 TRI.splitReg(DestReg, DestLo, DestHi); in copyPhysReg()
68 if (AVR::GPR8RegClass.contains(DestReg, SrcReg)) { in copyPhysReg()
70 } else if (SrcReg == AVR::SP && AVR::DREGSRegClass.contains(DestReg)) { in copyPhysReg()
72 } else if (DestReg == AVR::SP && AVR::DREGSRegClass.contains(SrcReg)) { in copyPhysReg()
78 BuildMI(MBB, MI, DL, get(Opc), DestReg) in copyPhysReg()
162 unsigned DestReg, int FrameIndex, in loadRegFromStackSlot() argument
189 BuildMI(MBB, MI, DL, get(Opcode), DestReg) in loadRegFromStackSlot()
/freebsd-12.1/contrib/llvm/lib/Target/PowerPC/
H A DPPCFastISel.cpp999 unsigned DestReg; in SelectFPTrunc() local
1004 TII.get(PPC::EFSCFD), DestReg) in SelectFPTrunc()
1009 TII.get(PPC::FRSP), DestReg) in SelectFPTrunc()
1013 updateValueMap(I, DestReg); in SelectFPTrunc()
1105 updateValueMap(I, DestReg); in SelectIToFP()
1150 updateValueMap(I, DestReg); in SelectIToFP()
1233 unsigned DestReg; in SelectFPToI() local
1843 DestReg) in PPCEmitIntExt()
2059 return DestReg; in PPCMaterializeFP()
2086 DestReg) in PPCMaterializeGV()
[all …]
/freebsd-12.1/contrib/llvm/lib/Target/XCore/
H A DXCoreInstrInfo.cpp334 const DebugLoc &DL, unsigned DestReg, in copyPhysReg() argument
336 bool GRDest = XCore::GRRegsRegClass.contains(DestReg); in copyPhysReg()
340 BuildMI(MBB, I, DL, get(XCore::ADD_2rus), DestReg) in copyPhysReg()
347 BuildMI(MBB, I, DL, get(XCore::LDAWSP_ru6), DestReg).addImm(0); in copyPhysReg()
351 if (DestReg == XCore::SP && GRSrc) { in copyPhysReg()
384 unsigned DestReg, int FrameIndex, in loadRegFromStackSlot() argument
397 BuildMI(MBB, I, DL, get(XCore::LDWFI), DestReg) in loadRegFromStackSlot()

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