Lines Matching refs:DestReg
2261 static bool forwardCopyWillClobberTuple(unsigned DestReg, unsigned SrcReg, in forwardCopyWillClobberTuple() argument
2265 return ((DestReg - SrcReg) & 0x1f) < NumRegs; in forwardCopyWillClobberTuple()
2270 const DebugLoc &DL, unsigned DestReg, in copyPhysRegTuple() argument
2276 uint16_t DestEncoding = TRI->getEncodingValue(DestReg); in copyPhysRegTuple()
2289 AddSubReg(MIB, DestReg, Indices[SubReg], RegState::Define, TRI); in copyPhysRegTuple()
2297 DebugLoc DL, unsigned DestReg, in copyGPRRegTuple() argument
2305 uint16_t DestEncoding = TRI->getEncodingValue(DestReg); in copyGPRRegTuple()
2313 AddSubReg(MIB, DestReg, Indices[SubReg], RegState::Define, TRI); in copyGPRRegTuple()
2322 const DebugLoc &DL, unsigned DestReg, in copyPhysReg() argument
2324 if (AArch64::GPR32spRegClass.contains(DestReg) && in copyPhysReg()
2328 if (DestReg == AArch64::WSP || SrcReg == AArch64::WSP) { in copyPhysReg()
2332 unsigned DestRegX = TRI->getMatchingSuperReg(DestReg, AArch64::sub_32, in copyPhysReg()
2346 BuildMI(MBB, I, DL, get(AArch64::ADDWri), DestReg) in copyPhysReg()
2352 BuildMI(MBB, I, DL, get(AArch64::MOVZWi), DestReg) in copyPhysReg()
2358 unsigned DestRegX = TRI->getMatchingSuperReg(DestReg, AArch64::sub_32, in copyPhysReg()
2372 BuildMI(MBB, I, DL, get(AArch64::ORRWrr), DestReg) in copyPhysReg()
2380 if (AArch64::GPR64spRegClass.contains(DestReg) && in copyPhysReg()
2382 if (DestReg == AArch64::SP || SrcReg == AArch64::SP) { in copyPhysReg()
2384 BuildMI(MBB, I, DL, get(AArch64::ADDXri), DestReg) in copyPhysReg()
2389 BuildMI(MBB, I, DL, get(AArch64::MOVZXi), DestReg) in copyPhysReg()
2394 BuildMI(MBB, I, DL, get(AArch64::ORRXrr), DestReg) in copyPhysReg()
2402 if (AArch64::DDDDRegClass.contains(DestReg) && in copyPhysReg()
2406 copyPhysRegTuple(MBB, I, DL, DestReg, SrcReg, KillSrc, AArch64::ORRv8i8, in copyPhysReg()
2412 if (AArch64::DDDRegClass.contains(DestReg) && in copyPhysReg()
2416 copyPhysRegTuple(MBB, I, DL, DestReg, SrcReg, KillSrc, AArch64::ORRv8i8, in copyPhysReg()
2422 if (AArch64::DDRegClass.contains(DestReg) && in copyPhysReg()
2425 copyPhysRegTuple(MBB, I, DL, DestReg, SrcReg, KillSrc, AArch64::ORRv8i8, in copyPhysReg()
2431 if (AArch64::QQQQRegClass.contains(DestReg) && in copyPhysReg()
2435 copyPhysRegTuple(MBB, I, DL, DestReg, SrcReg, KillSrc, AArch64::ORRv16i8, in copyPhysReg()
2441 if (AArch64::QQQRegClass.contains(DestReg) && in copyPhysReg()
2445 copyPhysRegTuple(MBB, I, DL, DestReg, SrcReg, KillSrc, AArch64::ORRv16i8, in copyPhysReg()
2451 if (AArch64::QQRegClass.contains(DestReg) && in copyPhysReg()
2454 copyPhysRegTuple(MBB, I, DL, DestReg, SrcReg, KillSrc, AArch64::ORRv16i8, in copyPhysReg()
2459 if (AArch64::XSeqPairsClassRegClass.contains(DestReg) && in copyPhysReg()
2462 copyGPRRegTuple(MBB, I, DL, DestReg, SrcReg, KillSrc, AArch64::ORRXrs, in copyPhysReg()
2467 if (AArch64::WSeqPairsClassRegClass.contains(DestReg) && in copyPhysReg()
2470 copyGPRRegTuple(MBB, I, DL, DestReg, SrcReg, KillSrc, AArch64::ORRWrs, in copyPhysReg()
2475 if (AArch64::FPR128RegClass.contains(DestReg) && in copyPhysReg()
2478 BuildMI(MBB, I, DL, get(AArch64::ORRv16i8), DestReg) in copyPhysReg()
2489 .addReg(DestReg, RegState::Define) in copyPhysReg()
2496 if (AArch64::FPR64RegClass.contains(DestReg) && in copyPhysReg()
2499 DestReg = RI.getMatchingSuperReg(DestReg, AArch64::dsub, in copyPhysReg()
2503 BuildMI(MBB, I, DL, get(AArch64::ORRv16i8), DestReg) in copyPhysReg()
2507 BuildMI(MBB, I, DL, get(AArch64::FMOVDr), DestReg) in copyPhysReg()
2513 if (AArch64::FPR32RegClass.contains(DestReg) && in copyPhysReg()
2516 DestReg = RI.getMatchingSuperReg(DestReg, AArch64::ssub, in copyPhysReg()
2520 BuildMI(MBB, I, DL, get(AArch64::ORRv16i8), DestReg) in copyPhysReg()
2524 BuildMI(MBB, I, DL, get(AArch64::FMOVSr), DestReg) in copyPhysReg()
2530 if (AArch64::FPR16RegClass.contains(DestReg) && in copyPhysReg()
2533 DestReg = RI.getMatchingSuperReg(DestReg, AArch64::hsub, in copyPhysReg()
2537 BuildMI(MBB, I, DL, get(AArch64::ORRv16i8), DestReg) in copyPhysReg()
2541 DestReg = RI.getMatchingSuperReg(DestReg, AArch64::hsub, in copyPhysReg()
2545 BuildMI(MBB, I, DL, get(AArch64::FMOVSr), DestReg) in copyPhysReg()
2551 if (AArch64::FPR8RegClass.contains(DestReg) && in copyPhysReg()
2554 DestReg = RI.getMatchingSuperReg(DestReg, AArch64::bsub, in copyPhysReg()
2558 BuildMI(MBB, I, DL, get(AArch64::ORRv16i8), DestReg) in copyPhysReg()
2562 DestReg = RI.getMatchingSuperReg(DestReg, AArch64::bsub, in copyPhysReg()
2566 BuildMI(MBB, I, DL, get(AArch64::FMOVSr), DestReg) in copyPhysReg()
2573 if (AArch64::FPR64RegClass.contains(DestReg) && in copyPhysReg()
2575 BuildMI(MBB, I, DL, get(AArch64::FMOVXDr), DestReg) in copyPhysReg()
2579 if (AArch64::GPR64RegClass.contains(DestReg) && in copyPhysReg()
2581 BuildMI(MBB, I, DL, get(AArch64::FMOVDXr), DestReg) in copyPhysReg()
2586 if (AArch64::FPR32RegClass.contains(DestReg) && in copyPhysReg()
2588 BuildMI(MBB, I, DL, get(AArch64::FMOVWSr), DestReg) in copyPhysReg()
2592 if (AArch64::GPR32RegClass.contains(DestReg) && in copyPhysReg()
2594 BuildMI(MBB, I, DL, get(AArch64::FMOVSWr), DestReg) in copyPhysReg()
2599 if (DestReg == AArch64::NZCV) { in copyPhysReg()
2609 assert(AArch64::GPR64RegClass.contains(DestReg) && "Invalid NZCV copy"); in copyPhysReg()
2610 BuildMI(MBB, I, DL, get(AArch64::MRS), DestReg) in copyPhysReg()
2752 unsigned DestReg, unsigned SubIdx0, in loadRegPairFromStackSlot() argument
2755 unsigned DestReg0 = DestReg; in loadRegPairFromStackSlot()
2756 unsigned DestReg1 = DestReg; in loadRegPairFromStackSlot()
2758 if (TargetRegisterInfo::isPhysicalRegister(DestReg)) { in loadRegPairFromStackSlot()
2759 DestReg0 = TRI.getSubReg(DestReg, SubIdx0); in loadRegPairFromStackSlot()
2761 DestReg1 = TRI.getSubReg(DestReg, SubIdx1); in loadRegPairFromStackSlot()
2774 MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, unsigned DestReg, in loadRegFromStackSlot() argument
2798 if (TargetRegisterInfo::isVirtualRegister(DestReg)) in loadRegFromStackSlot()
2799 MF.getRegInfo().constrainRegClass(DestReg, &AArch64::GPR32RegClass); in loadRegFromStackSlot()
2801 assert(DestReg != AArch64::WSP); in loadRegFromStackSlot()
2808 if (TargetRegisterInfo::isVirtualRegister(DestReg)) in loadRegFromStackSlot()
2809 MF.getRegInfo().constrainRegClass(DestReg, &AArch64::GPR64RegClass); in loadRegFromStackSlot()
2811 assert(DestReg != AArch64::SP); in loadRegFromStackSlot()
2816 get(AArch64::LDPWi), DestReg, AArch64::sube32, in loadRegFromStackSlot()
2830 get(AArch64::LDPXi), DestReg, AArch64::sube64, in loadRegFromStackSlot()
2871 .addReg(DestReg, getDefRegState(true)) in loadRegFromStackSlot()
2880 unsigned DestReg, unsigned SrcReg, int Offset, in emitFrameOffset() argument
2884 if (DestReg == SrcReg && Offset == 0) in emitFrameOffset()
2887 assert((DestReg != AArch64::SP || Offset % 16 == 0) && in emitFrameOffset()
2922 BuildMI(MBB, MBBI, DL, TII->get(Opc), DestReg) in emitFrameOffset()
2928 if (NeedsWinCFI && SrcReg == AArch64::SP && DestReg == AArch64::SP) in emitFrameOffset()
2933 SrcReg = DestReg; in emitFrameOffset()
2938 BuildMI(MBB, MBBI, DL, TII->get(Opc), DestReg) in emitFrameOffset()
2945 if ((DestReg == AArch64::FP && SrcReg == AArch64::SP) || in emitFrameOffset()
2946 (SrcReg == AArch64::FP && DestReg == AArch64::SP)) { in emitFrameOffset()
2953 } else if (DestReg == AArch64::SP) { in emitFrameOffset()