124                                   const DebugLoc &DL, unsigned DestReg,  in copyPhysReg()  argument
127   if (!ARM::GPRRegClass.contains(DestReg, SrcReg))  in copyPhysReg()
128     return ARMBaseInstrInfo::copyPhysReg(MBB, I, DL, DestReg, SrcReg, KillSrc);  in copyPhysReg()
130   BuildMI(MBB, I, DL, get(ARM::tMOVr), DestReg)  in copyPhysReg()
180                      unsigned DestReg, int FI,  in loadRegFromStackSlot()  argument
192     BuildMI(MBB, I, DL, get(ARM::t2LDRi12), DestReg)  in loadRegFromStackSlot()
204     if (TargetRegisterInfo::isVirtualRegister(DestReg)) {  in loadRegFromStackSlot()
206       MRI->constrainRegClass(DestReg,  in loadRegFromStackSlot()
211     AddDReg(MIB, DestReg, ARM::gsub_0, RegState::DefineNoRead, TRI);  in loadRegFromStackSlot()
212     AddDReg(MIB, DestReg, ARM::gsub_1, RegState::DefineNoRead, TRI);  in loadRegFromStackSlot()
215     if (TargetRegisterInfo::isPhysicalRegister(DestReg))  in loadRegFromStackSlot()
216       MIB.addReg(DestReg, RegState::ImplicitDefine);  in loadRegFromStackSlot()
220   ARMBaseInstrInfo::loadRegFromStackSlot(MBB, I, DestReg, FI, RC, TRI);  in loadRegFromStackSlot()
234                                   const DebugLoc &dl, unsigned DestReg,  in emitT2RegPlusImmediate()  argument
239   if (NumBytes == 0 && DestReg != BaseReg) {  in emitT2RegPlusImmediate()
240     BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVr), DestReg)  in emitT2RegPlusImmediate()
251   if (DestReg != ARM::SP && DestReg != BaseReg &&  in emitT2RegPlusImmediate()
257       BuildMI(MBB, MBBI, dl, TII.get(ARM::t2MOVi16), DestReg)  in emitT2RegPlusImmediate()
263       BuildMI(MBB, MBBI, dl, TII.get(ARM::t2MOVTi16), DestReg)  in emitT2RegPlusImmediate()
264         .addReg(DestReg)  in emitT2RegPlusImmediate()
272         BuildMI(MBB, MBBI, dl, TII.get(ARM::t2SUBrr), DestReg)  in emitT2RegPlusImmediate()
274             .addReg(DestReg, RegState::Kill)  in emitT2RegPlusImmediate()
284         BuildMI(MBB, MBBI, dl, TII.get(ARM::t2ADDrr), DestReg)  in emitT2RegPlusImmediate()
286             .addReg(DestReg, RegState::Kill)  in emitT2RegPlusImmediate()
298     if (DestReg == ARM::SP && BaseReg != ARM::SP) {  in emitT2RegPlusImmediate()
300       BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVr), DestReg)  in emitT2RegPlusImmediate()
311       if (DestReg == ARM::SP && (ThisVal < ((1 << 7)-1) * 4)) {  in emitT2RegPlusImmediate()
314         BuildMI(MBB, MBBI, dl, TII.get(Opc), DestReg)  in emitT2RegPlusImmediate()
336       assert(DestReg != ARM::SP && BaseReg != ARM::SP);  in emitT2RegPlusImmediate()
355     MachineInstrBuilder MIB = BuildMI(MBB, MBBI, dl, TII.get(Opc), DestReg)  in emitT2RegPlusImmediate()
363     BaseReg = DestReg;  in emitT2RegPlusImmediate()