86                                   const DebugLoc &DL, unsigned DestReg,  in copyPhysReg()  argument
91   if (Mips::GPR32RegClass.contains(DestReg)) { // Copy to CPU Reg.  in copyPhysReg()
112       BuildMI(MBB, I, DL, get(Mips::RDDSP), DestReg).addImm(1 << 4)  in copyPhysReg()
120     if (Mips::CCRRegClass.contains(DestReg))  in copyPhysReg()
122     else if (Mips::FGR32RegClass.contains(DestReg))  in copyPhysReg()
124     else if (Mips::HI32RegClass.contains(DestReg))  in copyPhysReg()
125       Opc = Mips::MTHI, DestReg = 0;  in copyPhysReg()
126     else if (Mips::LO32RegClass.contains(DestReg))  in copyPhysReg()
127       Opc = Mips::MTLO, DestReg = 0;  in copyPhysReg()
128     else if (Mips::HI32DSPRegClass.contains(DestReg))  in copyPhysReg()
130     else if (Mips::LO32DSPRegClass.contains(DestReg))  in copyPhysReg()
132     else if (Mips::DSPCCRegClass.contains(DestReg)) {  in copyPhysReg()
135         .addReg(DestReg, RegState::ImplicitDefine);  in copyPhysReg()
137     } else if (Mips::MSACtrlRegClass.contains(DestReg)) {  in copyPhysReg()
139           .addReg(DestReg)  in copyPhysReg()
144   else if (Mips::FGR32RegClass.contains(DestReg, SrcReg))  in copyPhysReg()
146   else if (Mips::AFGR64RegClass.contains(DestReg, SrcReg))  in copyPhysReg()
148   else if (Mips::FGR64RegClass.contains(DestReg, SrcReg))  in copyPhysReg()
150   else if (Mips::GPR64RegClass.contains(DestReg)) { // Copy to CPU64 Reg.  in copyPhysReg()
161     if (Mips::HI64RegClass.contains(DestReg))  in copyPhysReg()
162       Opc = Mips::MTHI64, DestReg = 0;  in copyPhysReg()
163     else if (Mips::LO64RegClass.contains(DestReg))  in copyPhysReg()
164       Opc = Mips::MTLO64, DestReg = 0;  in copyPhysReg()
165     else if (Mips::FGR64RegClass.contains(DestReg))  in copyPhysReg()
168   else if (Mips::MSA128BRegClass.contains(DestReg)) { // Copy to MSA reg  in copyPhysReg()
177   if (DestReg)  in copyPhysReg()
178     MIB.addReg(DestReg, RegState::Define);  in copyPhysReg()
326                  unsigned DestReg, int FI, const TargetRegisterClass *RC,  in loadRegFromStack()  argument
335                          (DestReg == Mips::LO0 || DestReg == Mips::LO0_64 ||  in loadRegFromStack()
336                           DestReg == Mips::HI0 || DestReg == Mips::HI0_64);  in loadRegFromStack()
381     BuildMI(MBB, I, DL, get(Opc), DestReg)  in loadRegFromStack()
390     if (DestReg == Mips::HI0)  in loadRegFromStack()
395       if (DestReg == Mips::HI0_64)  in loadRegFromStack()