Lines Matching refs:DestReg
771 unsigned DestReg, bool KillSrc, in copyFromCPSR() argument
778 BuildMI(MBB, I, I->getDebugLoc(), get(Opc), DestReg); in copyFromCPSR()
811 const DebugLoc &DL, unsigned DestReg, in copyPhysReg() argument
813 bool GPRDest = ARM::GPRRegClass.contains(DestReg); in copyPhysReg()
817 BuildMI(MBB, I, DL, get(ARM::MOVr), DestReg) in copyPhysReg()
824 bool SPRDest = ARM::SPRRegClass.contains(DestReg); in copyPhysReg()
834 else if (ARM::DPRRegClass.contains(DestReg, SrcReg) && !Subtarget.isFPOnlySP()) in copyPhysReg()
836 else if (ARM::QPRRegClass.contains(DestReg, SrcReg)) in copyPhysReg()
840 MachineInstrBuilder MIB = BuildMI(MBB, I, DL, get(Opc), DestReg); in copyPhysReg()
854 if (ARM::QQPRRegClass.contains(DestReg, SrcReg)) { in copyPhysReg()
858 } else if (ARM::QQQQPRRegClass.contains(DestReg, SrcReg)) { in copyPhysReg()
863 } else if (ARM::DPairRegClass.contains(DestReg, SrcReg)) { in copyPhysReg()
867 } else if (ARM::DTripleRegClass.contains(DestReg, SrcReg)) { in copyPhysReg()
871 } else if (ARM::DQuadRegClass.contains(DestReg, SrcReg)) { in copyPhysReg()
875 } else if (ARM::GPRPairRegClass.contains(DestReg, SrcReg)) { in copyPhysReg()
879 } else if (ARM::DPairSpcRegClass.contains(DestReg, SrcReg)) { in copyPhysReg()
884 } else if (ARM::DTripleSpcRegClass.contains(DestReg, SrcReg)) { in copyPhysReg()
889 } else if (ARM::DQuadSpcRegClass.contains(DestReg, SrcReg)) { in copyPhysReg()
894 } else if (ARM::DPRRegClass.contains(DestReg, SrcReg) && Subtarget.isFPOnlySP()) { in copyPhysReg()
899 copyFromCPSR(MBB, I, DestReg, KillSrc, Subtarget); in copyPhysReg()
901 } else if (DestReg == ARM::CPSR) { in copyPhysReg()
912 if (TRI->regsOverlap(SrcReg, TRI->getSubReg(DestReg, BeginIdx))) { in copyPhysReg()
920 unsigned Dst = TRI->getSubReg(DestReg, BeginIdx + i * Spacing); in copyPhysReg()
937 Mov->addRegisterDefined(DestReg, TRI); in copyPhysReg()
1191 unsigned DestReg, int FI, in loadRegFromStackSlot() argument
1206 BuildMI(MBB, I, DL, get(ARM::VLDRH), DestReg) in loadRegFromStackSlot()
1216 BuildMI(MBB, I, DL, get(ARM::LDRi12), DestReg) in loadRegFromStackSlot()
1222 BuildMI(MBB, I, DL, get(ARM::VLDRS), DestReg) in loadRegFromStackSlot()
1232 BuildMI(MBB, I, DL, get(ARM::VLDRD), DestReg) in loadRegFromStackSlot()
1242 AddDReg(MIB, DestReg, ARM::gsub_0, RegState::DefineNoRead, TRI); in loadRegFromStackSlot()
1243 AddDReg(MIB, DestReg, ARM::gsub_1, RegState::DefineNoRead, TRI); in loadRegFromStackSlot()
1253 MIB = AddDReg(MIB, DestReg, ARM::gsub_0, RegState::DefineNoRead, TRI); in loadRegFromStackSlot()
1254 MIB = AddDReg(MIB, DestReg, ARM::gsub_1, RegState::DefineNoRead, TRI); in loadRegFromStackSlot()
1257 if (TargetRegisterInfo::isPhysicalRegister(DestReg)) in loadRegFromStackSlot()
1258 MIB.addReg(DestReg, RegState::ImplicitDefine); in loadRegFromStackSlot()
1265 BuildMI(MBB, I, DL, get(ARM::VLD1q64), DestReg) in loadRegFromStackSlot()
1271 BuildMI(MBB, I, DL, get(ARM::VLDMQIA), DestReg) in loadRegFromStackSlot()
1282 BuildMI(MBB, I, DL, get(ARM::VLD1d64TPseudo), DestReg) in loadRegFromStackSlot()
1292 MIB = AddDReg(MIB, DestReg, ARM::dsub_0, RegState::DefineNoRead, TRI); in loadRegFromStackSlot()
1293 MIB = AddDReg(MIB, DestReg, ARM::dsub_1, RegState::DefineNoRead, TRI); in loadRegFromStackSlot()
1294 MIB = AddDReg(MIB, DestReg, ARM::dsub_2, RegState::DefineNoRead, TRI); in loadRegFromStackSlot()
1295 if (TargetRegisterInfo::isPhysicalRegister(DestReg)) in loadRegFromStackSlot()
1296 MIB.addReg(DestReg, RegState::ImplicitDefine); in loadRegFromStackSlot()
1304 BuildMI(MBB, I, DL, get(ARM::VLD1d64QPseudo), DestReg) in loadRegFromStackSlot()
1314 MIB = AddDReg(MIB, DestReg, ARM::dsub_0, RegState::DefineNoRead, TRI); in loadRegFromStackSlot()
1315 MIB = AddDReg(MIB, DestReg, ARM::dsub_1, RegState::DefineNoRead, TRI); in loadRegFromStackSlot()
1316 MIB = AddDReg(MIB, DestReg, ARM::dsub_2, RegState::DefineNoRead, TRI); in loadRegFromStackSlot()
1317 MIB = AddDReg(MIB, DestReg, ARM::dsub_3, RegState::DefineNoRead, TRI); in loadRegFromStackSlot()
1318 if (TargetRegisterInfo::isPhysicalRegister(DestReg)) in loadRegFromStackSlot()
1319 MIB.addReg(DestReg, RegState::ImplicitDefine); in loadRegFromStackSlot()
1330 MIB = AddDReg(MIB, DestReg, ARM::dsub_0, RegState::DefineNoRead, TRI); in loadRegFromStackSlot()
1331 MIB = AddDReg(MIB, DestReg, ARM::dsub_1, RegState::DefineNoRead, TRI); in loadRegFromStackSlot()
1332 MIB = AddDReg(MIB, DestReg, ARM::dsub_2, RegState::DefineNoRead, TRI); in loadRegFromStackSlot()
1333 MIB = AddDReg(MIB, DestReg, ARM::dsub_3, RegState::DefineNoRead, TRI); in loadRegFromStackSlot()
1334 MIB = AddDReg(MIB, DestReg, ARM::dsub_4, RegState::DefineNoRead, TRI); in loadRegFromStackSlot()
1335 MIB = AddDReg(MIB, DestReg, ARM::dsub_5, RegState::DefineNoRead, TRI); in loadRegFromStackSlot()
1336 MIB = AddDReg(MIB, DestReg, ARM::dsub_6, RegState::DefineNoRead, TRI); in loadRegFromStackSlot()
1337 MIB = AddDReg(MIB, DestReg, ARM::dsub_7, RegState::DefineNoRead, TRI); in loadRegFromStackSlot()
1338 if (TargetRegisterInfo::isPhysicalRegister(DestReg)) in loadRegFromStackSlot()
1339 MIB.addReg(DestReg, RegState::ImplicitDefine); in loadRegFromStackSlot()
1592 unsigned DestReg, unsigned SubIdx, in reMaterialize() argument
1599 MI->substituteRegister(Orig.getOperand(0).getReg(), DestReg, SubIdx, TRI); in reMaterialize()
1608 BuildMI(MBB, I, Orig.getDebugLoc(), get(Opcode), DestReg) in reMaterialize()
2116 unsigned DestReg = MI.getOperand(0).getReg(); in optimizeSelect() local
2118 if (!MRI.constrainRegClass(DestReg, PreviousClass)) in optimizeSelect()
2124 BuildMI(*MI.getParent(), MI, MI.getDebugLoc(), DefMI->getDesc(), DestReg); in optimizeSelect()
2225 const DebugLoc &dl, unsigned DestReg, in emitARMRegPlusImmediate() argument
2230 if (NumBytes == 0 && DestReg != BaseReg) { in emitARMRegPlusImmediate()
2231 BuildMI(MBB, MBBI, dl, TII.get(ARM::MOVr), DestReg) in emitARMRegPlusImmediate()
2254 BuildMI(MBB, MBBI, dl, TII.get(Opc), DestReg) in emitARMRegPlusImmediate()
2260 BaseReg = DestReg; in emitARMRegPlusImmediate()