| /llvm-project-15.0.7/llvm/lib/MC/ |
| H A D | MCRegisterInfo.cpp | 37 const uint16_t *SRI = SubRegIndices + get(Reg).SubRegIndices; in getSubReg() local
38 for (MCSubRegIterator Subs(Reg, this); Subs.isValid(); ++Subs, ++SRI) in getSubReg()
39 if (*SRI == Idx) in getSubReg()
49 const uint16_t *SRI = SubRegIndices + get(Reg).SubRegIndices; in getSubRegIndex() local
50 for (MCSubRegIterator Subs(Reg, this); Subs.isValid(); ++Subs, ++SRI) in getSubRegIndex()
52 return *SRI; in getSubRegIndex()
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| /llvm-project-15.0.7/llvm/lib/Target/Hexagon/MCTargetDesc/ |
| H A D | HexagonMCChecker.cpp | 83 SRI.isValid(); ++SRI) in initReg()
84 if (!MCSubRegIterator(*SRI, &RI).isValid()) in initReg()
86 Uses.insert(*SRI); in initReg()
152 SRI.isValid(); ++SRI) { in init()
153 if (MCSubRegIterator(*SRI, &RI).isValid()) in init()
157 if (R == *SRI) { in init()
166 if (Hexagon::P3_0 != R && Hexagon::P3_0 == *SRI) in init()
171 SoftDefs.insert(*SRI); in init()
175 LatePreds.insert(*SRI); in init()
183 TmpDefs.insert(*SRI); in init()
[all …]
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| /llvm-project-15.0.7/llvm/lib/Target/WebAssembly/ |
| H A D | WebAssemblyCFGSort.cpp | 223 SortRegionInfo SRI(MLI, WEI); in sortBlocks() local
226 const SortRegion *R = SRI.getRegionFor(MBB); in sortBlocks()
344 const SortRegion *Region = SRI.getRegionFor(&MBB); in sortBlocks()
370 assert(OnStack.count(SRI.getRegionFor(&MBB)) && in sortBlocks()
373 while (OnStack.size() > 1 && &MBB == SRI.getBottom(OnStack.back())) in sortBlocks()
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| H A D | WebAssemblyCFGStackify.cpp | 402 SortRegionInfo SRI(MLI, WEI); in placeLoopMarker() local
411 MachineBasicBlock *Bottom = SRI.getBottom(Loop); in placeLoopMarker()
472 SortRegionInfo SRI(MLI, WEI); in placeTryMarker() local
492 MachineBasicBlock *Bottom = SRI.getBottom(WE); in placeTryMarker()
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| /llvm-project-15.0.7/llvm/lib/CodeGen/ |
| H A D | CriticalAntiDepBreaker.cpp | 267 for (MCSubRegIterator SRI(PhysReg, TRI, true); SRI.isValid(); ++SRI) in ScanInstruction() local
268 if (!MO.clobbersPhysReg(*SRI)) in ScanInstruction()
300 for (MCSubRegIterator SRI(Reg, TRI, true); SRI.isValid(); ++SRI) { in ScanInstruction() local
301 unsigned SubregReg = *SRI; in ScanInstruction()
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| H A D | VirtRegMap.cpp | 323 LiveInterval::const_iterator &SRI = RangeIterPair.second; in addLiveInsForSubRanges() local
324 while (SRI != SR->end() && SRI->end <= MBBBegin) in addLiveInsForSubRanges()
325 ++SRI; in addLiveInsForSubRanges()
326 if (SRI == SR->end()) in addLiveInsForSubRanges()
328 if (SRI->start <= MBBBegin) in addLiveInsForSubRanges()
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| /llvm-project-15.0.7/llvm/lib/Target/AMDGPU/ |
| H A D | AMDGPUMachineCFGStructurizer.cpp | 2058 for (auto SRI = PHIInfo.sources_begin(DestReg); SRI != SE; ++SRI) { in prunePHIInfo() local
2059 unsigned SourceReg = (*SRI).first; in prunePHIInfo()
2069 for (auto SRI = PHIInfo.sources_begin(DestReg); SRI != SE; ++SRI) { in prunePHIInfo() local
2102 for (auto SRI = PHIInfo.sources_begin(DestReg); SRI != SE; ++SRI) { in createEntryPHI() local
2107 auto SRI = PHIInfo.sources_begin(DestReg); in createEntryPHI() local
2108 unsigned SourceReg = (*SRI).first; in createEntryPHI()
2118 for (auto SRI = PHIInfo.sources_begin(DestReg); SRI != SE; ++SRI) { in createEntryPHI() local
2119 unsigned SourceReg = (*SRI).first; in createEntryPHI()
2136 BackedgePHI.addMBB((*SRI).second); in createEntryPHI()
2148 MIB.addMBB((*SRI).second); in createEntryPHI()
[all …]
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| H A D | GCNSchedStrategy.cpp | 76 const SIRegisterInfo *SRI, in initCandidate() argument
163 const SIRegisterInfo *SRI = static_cast<const SIRegisterInfo*>(TRI); in pickNodeFromQueue() local
171 initCandidate(TryCand, SU, Zone.isTop(), RPTracker, SRI, in pickNodeFromQueue()
884 const SIRegisterInfo *SRI = static_cast<const SIRegisterInfo *>(DAG.TRI); in collectRematerializableInstructions() local
891 if (!SRI->isVGPRClass(DAG.MRI.getRegClass(Reg)) || in collectRematerializableInstructions()
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| H A D | GCNSchedStrategy.h | 39 const SIRegisterInfo *SRI,
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| H A D | SIFoldOperands.cpp | 437 const SIRegisterInfo &SRI = TII->getRegisterInfo(); in tryAddToFoldList() local
441 if (!SRI.opCanUseInlineConstant(OpInfo.OperandType) || in tryAddToFoldList()
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| /llvm-project-15.0.7/llvm/lib/CodeGen/LiveDebugValues/ |
| H A D | InstrRefBasedImpl.cpp | 1238 for (MCSubRegIterator SRI(Reg, TRI, false); SRI.isValid(); ++SRI) { in transferDebugInstrRef() local
1243 NewReg = *SRI; in transferDebugInstrRef()
1523 for (MCSubRegIndexIterator SRI(SrcRegNum, TRI); SRI.isValid(); ++SRI) { in performCopy() local
1524 unsigned SrcSubReg = SRI.getSubReg(); in performCopy()
1525 unsigned SubRegIdx = SRI.getSubRegIndex(); in performCopy()
1657 for (MCSubRegIterator SRI(Reg, TRI, false); SRI.isValid(); ++SRI) { in transferSpillOrRestoreInst() local
1659 (void)MTracker->lookupOrTrackRegister(*SRI); in transferSpillOrRestoreInst()
1662 DoTransfer(*SRI, SpillID); in transferSpillOrRestoreInst()
1692 for (MCSubRegIterator SRI(Reg, TRI, false); SRI.isValid(); ++SRI) { in transferSpillOrRestoreInst() local
1693 unsigned Subreg = TRI->getSubRegIndex(Reg, *SRI); in transferSpillOrRestoreInst()
[all …]
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| /llvm-project-15.0.7/llvm/utils/TableGen/ |
| H A D | CodeGenRegisters.cpp | 134 for (CodeGenSubRegIndex *SRI : SubIdx->ConcatenationOf) in computeConcatTransitiveClosure()
318 SubRegMap::const_iterator SRI = Map.find(Comp.first); in computeSubRegs() local
319 if (SRI == Map.end()) in computeSubRegs()
323 if (SubRegs.count(Comp.second) || !Orphans.erase(SRI->second)) in computeSubRegs()
326 SubRegs.insert(std::make_pair(Comp.second, SRI->second)); in computeSubRegs()
1204 for (CodeGenSubRegIndex &SRI : SubRegIndices) { in CodeGenRegBank()
1205 SRI.computeConcatTransitiveClosure(); in CodeGenRegBank()
1206 if (!SRI.ConcatenationOf.empty()) in CodeGenRegBank()
1209 SRI.ConcatenationOf.end()), &SRI)); in CodeGenRegBank()
1775 for (auto SRI : SRM) { in normalizeWeight() local
[all …]
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| H A D | RegisterInfoEmitter.cpp | 1766 for (const CodeGenSubRegIndex &SRI : RegBank.getSubRegIndices()) { in debugDump() local
1767 OS << "SubRegIndex " << SRI.getName() << ":\n"; in debugDump()
1768 OS << "\tLaneMask: " << PrintLaneMask(SRI.LaneMask) << '\n'; in debugDump()
1769 OS << "\tAllSuperRegsCovered: " << SRI.AllSuperRegsCovered << '\n'; in debugDump()
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| H A D | GlobalISelEmitter.cpp | 2919 SubRegIndexRenderer(unsigned InsnID, const CodeGenSubRegIndex *SRI) in SubRegIndexRenderer() argument
2920 : OperandRenderer(OR_SubRegIndex), InsnID(InsnID), SubRegIdx(SRI) {} in SubRegIndexRenderer()
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| /llvm-project-15.0.7/llvm/lib/Target/PowerPC/ |
| H A D | PPCISelDAGToDAG.cpp | 5598 unsigned SRI; in Select() local
5601 case 0: SRI = PPC::sub_lt; break; in Select()
5602 case 1: SRI = PPC::sub_gt; break; in Select()
5603 case 2: SRI = PPC::sub_eq; break; in Select()
5604 case 3: SRI = PPC::sub_un; break; in Select()
5607 SDValue CCBit = CurDAG->getTargetExtractSubreg(SRI, dl, MVT::i1, CCReg); in Select()
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| /llvm-project-15.0.7/llvm/lib/Target/AArch64/ |
| H A D | AArch64SchedCyclone.td | 501 // SLI,SRI
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| H A D | AArch64SchedNeoverseN2.td | 1615 (instregex "^(SHRNB|SHRNT|SSHLLB|SSHLLT|USHLLB|USHLLT|SLI|SRI)_ZZI_[BHSD]$")>;
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| H A D | AArch64InstrInfo.td | 6624 defm SRI : SIMDScalarRShiftDTied< 1, 0b01000, "sri">;
6673 defm SRI : SIMDVectorRShiftBHSDTied<1, 0b01000, "sri", AArch64vsri>;
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| /llvm-project-15.0.7/llvm/test/CodeGen/AArch64/ |
| H A D | sve2-intrinsics-uniform-dsp.ll | 1255 ; SRI
|