| /llvm-project-15.0.7/llvm/lib/Target/AArch64/ |
| H A D | AArch64RegisterInfo.td | 1108 def ZPR#RegWidth#AsmOpndExtUXTW8 : ZPRExtendAsmOperand<"UXTW", RegWidth, 8>;
1109 def ZPR#RegWidth#AsmOpndExtUXTW16 : ZPRExtendAsmOperand<"UXTW", RegWidth, 16>;
1110 def ZPR#RegWidth#AsmOpndExtUXTW32 : ZPRExtendAsmOperand<"UXTW", RegWidth, 32>;
1111 def ZPR#RegWidth#AsmOpndExtUXTW64 : ZPRExtendAsmOperand<"UXTW", RegWidth, 64>;
1121 def ZPR#RegWidth#AsmOpndExtSXTW8 : ZPRExtendAsmOperand<"SXTW", RegWidth, 8>;
1122 def ZPR#RegWidth#AsmOpndExtSXTW16 : ZPRExtendAsmOperand<"SXTW", RegWidth, 16>;
1123 def ZPR#RegWidth#AsmOpndExtSXTW32 : ZPRExtendAsmOperand<"SXTW", RegWidth, 32>;
1133 def ZPR#RegWidth#AsmOpndExtLSL8 : ZPRExtendAsmOperand<"LSL", RegWidth, 8>;
1134 def ZPR#RegWidth#AsmOpndExtLSL16 : ZPRExtendAsmOperand<"LSL", RegWidth, 16>;
1135 def ZPR#RegWidth#AsmOpndExtLSL32 : ZPRExtendAsmOperand<"LSL", RegWidth, 32>;
[all …]
|
| H A D | AArch64ISelDAGToDAG.cpp | 397 template<unsigned RegWidth>
399 return SelectCVTFixedPosOperand(N, FixedPos, RegWidth); in SelectCVTFixedPosOperand()
2997 unsigned RegWidth) { in SelectCVTFixedPosOperand() argument
3033 if (FBits == 0 || FBits > RegWidth) return false; in SelectCVTFixedPosOperand()
|
| /llvm-project-15.0.7/llvm/lib/Target/AArch64/MCTargetDesc/ |
| H A D | AArch64AddressingModes.h | 810 inline static bool isAnyMOVZMovAlias(uint64_t Value, int RegWidth) { in isAnyMOVZMovAlias() argument
811 for (int Shift = 0; Shift <= RegWidth - 16; Shift += 16) in isAnyMOVZMovAlias()
818 inline static bool isMOVZMovAlias(uint64_t Value, int Shift, int RegWidth) { in isMOVZMovAlias() argument
819 if (RegWidth == 32) in isMOVZMovAlias()
831 if (isAnyMOVZMovAlias(Value, RegWidth)) in isMOVNMovAlias()
835 if (RegWidth == 32) in isMOVNMovAlias()
838 return isMOVZMovAlias(Value, Shift, RegWidth); in isMOVNMovAlias()
841 inline static bool isAnyMOVWMovAlias(uint64_t Value, int RegWidth) { in isAnyMOVWMovAlias() argument
842 if (isAnyMOVZMovAlias(Value, RegWidth)) in isAnyMOVWMovAlias()
847 if (RegWidth == 32) in isAnyMOVWMovAlias()
[all …]
|
| H A D | AArch64InstPrinter.cpp | 246 int RegWidth = Opcode == AArch64::MOVZXi ? 64 : 32; in printInst() local
253 << formatImm(SignExtend64(Value, RegWidth)); in printInst()
260 int RegWidth = Opcode == AArch64::MOVNXi ? 64 : 32; in printInst() local
263 if (RegWidth == 32) in printInst()
266 if (AArch64_AM::isMOVNMovAlias(Value, Shift, RegWidth)) { in printInst()
268 << formatImm(SignExtend64(Value, RegWidth)); in printInst()
277 int RegWidth = Opcode == AArch64::ORRXri ? 64 : 32; in printInst() local
279 MI->getOperand(2).getImm(), RegWidth); in printInst()
280 if (!AArch64_AM::isAnyMOVWMovAlias(Value, RegWidth)) { in printInst()
282 << formatImm(SignExtend64(Value, RegWidth)); in printInst()
|
| /llvm-project-15.0.7/llvm/lib/Target/Hexagon/ |
| H A D | HexagonTargetTransformInfo.cpp | 178 unsigned RegWidth = in getMemoryOpCost() local
181 assert(RegWidth && "Non-zero vector register width expected"); in getMemoryOpCost()
183 if (VecWidth % RegWidth == 0) in getMemoryOpCost()
184 return VecWidth / RegWidth; in getMemoryOpCost()
186 const Align RegAlign(RegWidth / 8); in getMemoryOpCost()
|
| /llvm-project-15.0.7/llvm/lib/Target/AMDGPU/AsmParser/ |
| H A D | AMDGPUAsmParser.cpp | 2321 switch (RegWidth) { in getRegClass()
2345 switch (RegWidth) { in getRegClass()
2489 RegWidth = 64; in AddNextRegisterToList()
2494 RegWidth = 64; in AddNextRegisterToList()
2499 RegWidth = 64; in AddNextRegisterToList()
2504 RegWidth = 64; in AddNextRegisterToList()
2509 RegWidth = 64; in AddNextRegisterToList()
2514 RegWidth = 64; in AddNextRegisterToList()
2527 RegWidth += 32; in AddNextRegisterToList()
2690 RegWidth = 32; in ParseSpecialReg()
[all …]
|
| /llvm-project-15.0.7/llvm/lib/Target/AArch64/AsmParser/ |
| H A D | AArch64AsmParser.cpp | 5530 uint64_t RegWidth = 0; in MatchAndEmitInstruction() local
5533 RegWidth = 64; in MatchAndEmitInstruction()
5535 RegWidth = 32; in MatchAndEmitInstruction()
5537 if (LSB >= RegWidth) in MatchAndEmitInstruction()
5545 if (RegWidth == 32) in MatchAndEmitInstruction()
5586 uint64_t RegWidth = 0; in MatchAndEmitInstruction() local
5589 RegWidth = 64; in MatchAndEmitInstruction()
5591 RegWidth = 32; in MatchAndEmitInstruction()
5601 if (RegWidth == 32) in MatchAndEmitInstruction()
5653 RegWidth = 64; in MatchAndEmitInstruction()
[all …]
|
| /llvm-project-15.0.7/llvm/lib/Target/AMDGPU/ |
| H A D | SIRegisterInfo.cpp | 1293 const unsigned RegWidth = AMDGPU::getRegBitWidth(RC->getID()) / 8; in buildSpillLoadStore() local
1297 unsigned EltSize = (IsFlat && !IsAGPR) ? std::min(RegWidth, 16u) : 4u; in buildSpillLoadStore()
1298 unsigned NumSubRegs = RegWidth / EltSize; in buildSpillLoadStore()
1300 unsigned RemSize = RegWidth - Size; in buildSpillLoadStore()
|
| /llvm-project-15.0.7/llvm/include/llvm/CodeGen/ |
| H A D | TargetLowering.h | 1566 unsigned RegWidth = getRegisterType(Context, VT).getSizeInBits(); variable
1567 return (BitWidth + RegWidth - 1) / RegWidth;
|
| /llvm-project-15.0.7/llvm/lib/CodeGen/ |
| H A D | CodeGenPrepare.cpp | 7025 unsigned RegWidth = RegType.getSizeInBits(); in optimizeSwitchType() local
7027 if (RegWidth <= cast<IntegerType>(OldType)->getBitWidth()) in optimizeSwitchType()
7036 auto *NewType = Type::getIntNTy(Context, RegWidth); in optimizeSwitchType()
7061 NarrowConst.zext(RegWidth) : NarrowConst.sext(RegWidth); in optimizeSwitchType()
|