Lines Matching refs:RegWidth
1070 template<int RegWidth, int Shift>
1078 return AArch64_AM::isMOVZMovAlias(Value, Shift, RegWidth); in isMOVZMovAlias()
1085 template<int RegWidth, int Shift>
1093 return AArch64_AM::isMOVNMovAlias(Value, Shift, RegWidth); in isMOVNMovAlias()
5530 uint64_t RegWidth = 0; in MatchAndEmitInstruction() local
5533 RegWidth = 64; in MatchAndEmitInstruction()
5535 RegWidth = 32; in MatchAndEmitInstruction()
5537 if (LSB >= RegWidth) in MatchAndEmitInstruction()
5540 if (Width < 1 || Width > RegWidth) in MatchAndEmitInstruction()
5545 if (RegWidth == 32) in MatchAndEmitInstruction()
5561 RegWidth == 32 ? AArch64::WZR : AArch64::XZR, RegKind::Scalar, in MatchAndEmitInstruction()
5586 uint64_t RegWidth = 0; in MatchAndEmitInstruction() local
5589 RegWidth = 64; in MatchAndEmitInstruction()
5591 RegWidth = 32; in MatchAndEmitInstruction()
5593 if (Op3Val >= RegWidth) in MatchAndEmitInstruction()
5596 if (Op4Val < 1 || Op4Val > RegWidth) in MatchAndEmitInstruction()
5601 if (RegWidth == 32) in MatchAndEmitInstruction()
5650 uint64_t RegWidth = 0; in MatchAndEmitInstruction() local
5653 RegWidth = 64; in MatchAndEmitInstruction()
5655 RegWidth = 32; in MatchAndEmitInstruction()
5657 if (Op3Val >= RegWidth) in MatchAndEmitInstruction()
5660 if (Op4Val < 1 || Op4Val > RegWidth) in MatchAndEmitInstruction()
5666 if (NewOp4Val >= RegWidth || NewOp4Val < Op3Val) in MatchAndEmitInstruction()