Lines Matching refs:RegWidth

1220                     unsigned RegWidth) {  in usesRegister()  argument
1223 usesSgprAt(DwordRegIndex + divideCeil(RegWidth, 32) - 1); in usesRegister()
1226 usesAgprAt(DwordRegIndex + divideCeil(RegWidth, 32) - 1); in usesRegister()
1229 usesVgprAt(DwordRegIndex + divideCeil(RegWidth, 32) - 1); in usesRegister()
1305 bool AddNextRegisterToList(unsigned& Reg, unsigned& RegWidth,
1308 unsigned &RegNum, unsigned &RegWidth,
1311 unsigned &RegNum, unsigned &RegWidth,
1314 unsigned &RegWidth,
1317 unsigned &RegWidth,
1320 unsigned &RegWidth, SmallVectorImpl<AsmToken> &Tokens);
1324 unsigned RegWidth,
1332 unsigned RegWidth);
2319 static int getRegClass(RegisterKind Is, unsigned RegWidth) { in getRegClass() argument
2321 switch (RegWidth) { in getRegClass()
2345 switch (RegWidth) { in getRegClass()
2359 switch (RegWidth) { in getRegClass()
2381 switch (RegWidth) { in getRegClass()
2482 bool AMDGPUAsmParser::AddNextRegisterToList(unsigned &Reg, unsigned &RegWidth, in AddNextRegisterToList() argument
2489 RegWidth = 64; in AddNextRegisterToList()
2494 RegWidth = 64; in AddNextRegisterToList()
2499 RegWidth = 64; in AddNextRegisterToList()
2504 RegWidth = 64; in AddNextRegisterToList()
2509 RegWidth = 64; in AddNextRegisterToList()
2514 RegWidth = 64; in AddNextRegisterToList()
2523 if (Reg1 != Reg + RegWidth / 32) { in AddNextRegisterToList()
2527 RegWidth += 32; in AddNextRegisterToList()
2607 unsigned RegWidth, in getRegularReg() argument
2616 AlignSize = std::min(RegWidth / 32, 4u); in getRegularReg()
2625 int RCID = getRegClass(RegKind, RegWidth); in getRegularReg()
2641 bool AMDGPUAsmParser::ParseRegRange(unsigned &Num, unsigned &RegWidth) { in ParseRegRange() argument
2679 RegWidth = 32 * ((RegHi - RegLo) + 1); in ParseRegRange()
2684 unsigned &RegNum, unsigned &RegWidth, in ParseSpecialReg() argument
2690 RegWidth = 32; in ParseSpecialReg()
2699 unsigned &RegNum, unsigned &RegWidth, in ParseRegularReg() argument
2722 RegWidth = 32; in ParseRegularReg()
2725 if (!ParseRegRange(RegNum, RegWidth)) in ParseRegularReg()
2729 return getRegularReg(RegKind, RegNum, RegWidth, Loc); in ParseRegularReg()
2733 unsigned &RegWidth, in ParseRegList() argument
2746 if (!ParseAMDGPURegister(RegKind, Reg, RegNum, RegWidth)) in ParseRegList()
2748 if (RegWidth != 32) { in ParseRegList()
2771 if (!AddNextRegisterToList(Reg, RegWidth, RegKind, NextReg, Loc)) in ParseRegList()
2781 Reg = getRegularReg(RegKind, RegNum, RegWidth, ListLoc); in ParseRegList()
2787 unsigned &RegNum, unsigned &RegWidth, in ParseAMDGPURegister() argument
2793 Reg = ParseSpecialReg(RegKind, RegNum, RegWidth, Tokens); in ParseAMDGPURegister()
2795 Reg = ParseRegularReg(RegKind, RegNum, RegWidth, Tokens); in ParseAMDGPURegister()
2797 Reg = ParseRegList(RegKind, RegNum, RegWidth, Tokens); in ParseAMDGPURegister()
2819 unsigned &RegNum, unsigned &RegWidth, in ParseAMDGPURegister() argument
2824 if (ParseAMDGPURegister(RegKind, Reg, RegNum, RegWidth, Tokens)) { in ParseAMDGPURegister()
2856 unsigned RegWidth) { in updateGprCountSymbols() argument
2866 int64_t NewMax = DwordRegIndex + divideCeil(RegWidth, 32) - 1; in updateGprCountSymbols()
2889 unsigned Reg, RegNum, RegWidth; in parseRegister() local
2891 if (!ParseAMDGPURegister(RegKind, Reg, RegNum, RegWidth)) { in parseRegister()
2895 if (!updateGprCountSymbols(RegKind, RegNum, RegWidth)) in parseRegister()
2898 KernelScope.usesRegister(RegKind, RegNum, RegWidth); in parseRegister()