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/llvm-project-15.0.7/llvm/lib/Target/Hexagon/
H A DHexagonDepMapAsm2Intrin.td14 def: Pat<(int_hexagon_A2_abs IntRegs:$src1),
15 (A2_abs IntRegs:$src1)>, Requires<[HasV5]>;
16 def: Pat<(int_hexagon_A2_absp DoubleRegs:$src1),
18 def: Pat<(int_hexagon_A2_abssat IntRegs:$src1),
62 def: Pat<(int_hexagon_A2_aslh IntRegs:$src1),
64 def: Pat<(int_hexagon_A2_asrh IntRegs:$src1),
110 def: Pat<(int_hexagon_A2_satb IntRegs:$src1),
112 def: Pat<(int_hexagon_A2_sath IntRegs:$src1),
176 def: Pat<(int_hexagon_A2_tfr IntRegs:$src1),
1809 def: Pat<(int_hexagon_V6_hi HvxWR:$src1),
[all …]
H A DHexagonMapAsm2IntrinV62.gen.td10 def: Pat<(IntID HvxVR:$src1, IntRegs:$src2),
11 (MI HvxVR:$src1, IntRegs:$src2)>;
13 (MI HvxVR:$src1, IntRegs:$src2)>;
25 def: Pat<(IntID HvxVR:$src1, HvxVR:$src2),
26 (MI HvxVR:$src1, HvxVR:$src2)>;
28 (MI HvxVR:$src1, HvxVR:$src2)>;
33 (MI HvxWR:$src1, HvxWR:$src2)>;
35 (MI HvxWR:$src1, HvxWR:$src2)>;
92 def: Pat<(IntID IntRegs:$src1),
93 (MI IntRegs:$src1)>;
[all …]
H A DHexagonIntrinsicsV60.td85 def: Pat<(IntID IntRegs:$src1), (MI IntRegs:$src1)>;
87 (MI IntRegs:$src1)>;
91 def: Pat<(IntID HvxVR:$src1),
92 (MI HvxVR:$src1)>;
95 (MI HvxVR:$src1)>;
99 def: Pat<(IntID HvxWR:$src1),
100 (MI HvxWR:$src1)>;
103 (MI HvxWR:$src1)>;
107 def: Pat<(IntID HvxQR:$src1),
108 (MI HvxQR:$src1)>;
[all …]
/llvm-project-15.0.7/clang/lib/Headers/
H A Damxintrin.h152 __builtin_ia32_tdpbssd((dst), (src0), (src1))
171 __builtin_ia32_tdpbsud((dst), (src0), (src1))
190 __builtin_ia32_tdpbusd((dst), (src0), (src1))
209 __builtin_ia32_tdpbuud((dst), (src0), (src1))
227 __builtin_ia32_tdpbf16ps((dst), (src0), (src1))
361 __tile1024i src1) { in __tile_dpbssd() argument
363 src0.tile, src1.tile); in __tile_dpbssd()
384 __tile1024i src1) { in __tile_dpbsud() argument
386 src0.tile, src1.tile); in __tile_dpbsud()
407 __tile1024i src1) { in __tile_dpbusd() argument
[all …]
/llvm-project-15.0.7/llvm/lib/Target/X86/
H A DX86InstrXOP.td174 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
181 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
251 "\t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}"),
259 "\t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}"),
287 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
295 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
303 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
334 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
343 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
349 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
[all …]
H A DX86InstrShiftRotate.td522 "rol{b}\t{$src1, $dst|$dst, $src1}",
525 "rol{w}\t{$src1, $dst|$dst, $src1}",
529 "rol{l}\t{$src1, $dst|$dst, $src1}",
533 "rol{q}\t{$src1, $dst|$dst, $src1}",
812 def : Pat<(rotl GR8:$src1, (i8 7)), (ROR8r1 GR8:$src1)>;
813 def : Pat<(rotl GR16:$src1, (i8 15)), (ROR16r1 GR16:$src1)>;
814 def : Pat<(rotl GR32:$src1, (i8 31)), (ROR32r1 GR32:$src1)>;
815 def : Pat<(rotl GR64:$src1, (i8 63)), (ROR64r1 GR64:$src1)>;
816 def : Pat<(rotr GR8:$src1, (i8 7)), (ROL8r1 GR8:$src1)>;
817 def : Pat<(rotr GR16:$src1, (i8 15)), (ROL16r1 GR16:$src1)>;
[all …]
H A DX86InstrKL.td20 def LOADIWKEY : I<0xDC, MRMSrcReg, (outs), (ins VR128:$src1, VR128:$src2),
21 "loadiwkey\t{$src2, $src1|$src1, $src2}",
38 let Constraints = "$src1 = $dst",
41 "aesenc128kl\t{$src2, $src1|$src1, $src2}",
43 (X86aesenc128kl VR128:$src1, addr:$src2))]>, T8XS,
47 "aesdec128kl\t{$src2, $src1|$src1, $src2}",
49 (X86aesdec128kl VR128:$src1, addr:$src2))]>, T8XS,
53 "aesenc256kl\t{$src2, $src1|$src1, $src2}",
55 (X86aesenc256kl VR128:$src1, addr:$src2))]>, T8XS,
59 "aesdec256kl\t{$src2, $src1|$src1, $src2}",
[all …]
H A DX86InstrSSE.td5677 "vptest\t{$src2, $src1|$src1, $src2}",
5681 "vptest\t{$src2, $src1|$src1, $src2}",
5687 "vptest\t{$src2, $src1|$src1, $src2}",
5691 "vptest\t{$src2, $src1|$src1, $src2}",
5699 "ptest\t{$src2, $src1|$src1, $src2}",
5703 "ptest\t{$src2, $src1|$src1, $src2}",
6648 !strconcat(asm, "\t{$src2, $src1|$src1, $src2}"),
6820 "vaesimc\t{$src1, $dst|$dst, $src1}",
6826 "vaesimc\t{$src1, $dst|$dst, $src1}",
6832 "aesimc\t{$src1, $dst|$dst, $src1}",
[all …]
/llvm-project-15.0.7/llvm/test/CodeGen/SystemZ/
H A Dint-cmp-38.ll10 define dso_local i32 @f1(i32 %src1) {
17 %cond = icmp slt i32 %src1, %src2
20 %mul = mul i32 %src1, %src1
35 %cond = icmp ult i32 %src1, %src2
38 %mul = mul i32 %src1, %src1
53 %cond = icmp eq i32 %src1, %src2
56 %mul = mul i32 %src1, %src1
74 %mul = mul i32 %src1, %src1
93 %mul = mul i32 %src1, %src1
112 %mul = mul i32 %src1, %src1
[all …]
H A Dint-cmp-43.ll10 define dso_local i64 @f1(i64 %src1) {
17 %cond = icmp slt i64 %src1, %src2
20 %mul = mul i64 %src1, %src1
35 %cond = icmp ult i64 %src1, %src2
38 %mul = mul i64 %src1, %src1
53 %cond = icmp eq i64 %src1, %src2
56 %mul = mul i64 %src1, %src1
71 %cond = icmp ne i64 %src1, %src2
74 %mul = mul i64 %src1, %src1
93 %mul = mul i64 %src1, %src1
[all …]
H A Dint-cmp-39.ll10 define dso_local i64 @f1(i64 %src1) {
18 %cond = icmp slt i64 %src1, %src2
21 %mul = mul i64 %src1, %src1
36 %cond = icmp ult i64 %src1, %src2
39 %mul = mul i64 %src1, %src1
55 %cond = icmp eq i64 %src1, %src2
58 %mul = mul i64 %src1, %src1
74 %cond = icmp ne i64 %src1, %src2
77 %mul = mul i64 %src1, %src1
97 %mul = mul i64 %src1, %src1
[all …]
H A Dint-cmp-42.ll10 define dso_local i64 @f1(i64 %src1) {
18 %cond = icmp ult i64 %src1, %src2
21 %mul = mul i64 %src1, %src1
36 %cond = icmp slt i64 %src1, %src2
39 %mul = mul i64 %src1, %src1
55 %cond = icmp eq i64 %src1, %src2
58 %mul = mul i64 %src1, %src1
74 %cond = icmp ne i64 %src1, %src2
77 %mul = mul i64 %src1, %src1
97 %mul = mul i64 %src1, %src1
[all …]
H A Dint-cmp-41.ll10 define dso_local i64 @f1(i64 %src1) {
18 %cond = icmp slt i64 %src1, %src2
21 %mul = mul i64 %src1, %src1
36 %cond = icmp ult i64 %src1, %src2
39 %mul = mul i64 %src1, %src1
55 %cond = icmp eq i64 %src1, %src2
58 %mul = mul i64 %src1, %src1
74 %cond = icmp ne i64 %src1, %src2
77 %mul = mul i64 %src1, %src1
97 %mul = mul i64 %src1, %src1
[all …]
H A Dint-cmp-36.ll10 define dso_local i32 @f1(i32 %src1) {
18 %cond = icmp slt i32 %src1, %src2
21 %mul = mul i32 %src1, %src1
36 %cond = icmp ult i32 %src1, %src2
39 %mul = mul i32 %src1, %src1
55 %cond = icmp eq i32 %src1, %src2
58 %mul = mul i32 %src1, %src1
74 %cond = icmp ne i32 %src1, %src2
77 %mul = mul i32 %src1, %src1
97 %mul = mul i32 %src1, %src1
[all …]
H A Dint-cmp-40.ll10 define dso_local i64 @f1(i64 %src1) {
18 %cond = icmp ult i64 %src1, %src2
21 %mul = mul i64 %src1, %src1
37 %cond = icmp slt i64 %src1, %src2
40 %mul = mul i64 %src1, %src1
57 %cond = icmp eq i64 %src1, %src2
60 %mul = mul i64 %src1, %src1
77 %cond = icmp ne i64 %src1, %src2
80 %mul = mul i64 %src1, %src1
101 %mul = mul i64 %src1, %src1
[all …]
H A Dint-cmp-37.ll10 define dso_local i32 @f1(i32 %src1) {
18 %cond = icmp ult i32 %src1, %src2
21 %mul = mul i32 %src1, %src1
37 %cond = icmp slt i32 %src1, %src2
40 %mul = mul i32 %src1, %src1
57 %cond = icmp eq i32 %src1, %src2
60 %mul = mul i32 %src1, %src1
77 %cond = icmp ne i32 %src1, %src2
80 %mul = mul i32 %src1, %src1
101 %mul = mul i32 %src1, %src1
[all …]
/llvm-project-15.0.7/llvm/test/CodeGen/AMDGPU/
H A Dmad-mix.ll13 %src1.ext = fpext half %src1 to float
25 %src1.hi = lshr i32 %src1, 16
28 %src1.i16 = trunc i32 %src1.hi to i16
31 %src1.fp16 = bitcast i16 %src1.i16 to half
50 %src1.ext = fpext half %src1.hi to float
110 %src1.ext = fpext half %src1 to float
124 %src1.ext = fpext half %src1 to float
143 %src1.ext = fpext half %src1 to float
160 %src1.ext = fpext half %src1 to float
174 %src1.ext = fpext half %src1 to float
[all …]
H A Dfdot2.ll28 %src1.vec = load <2 x half>, <2 x half> addrspace(1)* %src1
31 %src1.el1 = extractelement <2 x half> %src1.vec, i64 0
34 %src1.el2 = extractelement <2 x half> %src1.vec, i64 1
69 %src1.el1 = extractelement <2 x half> %src1.vec, i64 0
74 %src1.el2 = extractelement <2 x half> %src1.vec, i64 1
109 %src1.el1 = extractelement <2 x half> %src1.vec, i64 0
114 %src1.el2 = extractelement <2 x half> %src1.vec, i64 1
146 %src1.el1 = extractelement <4 x half> %src1.vec, i64 0
151 %src1.el2 = extractelement <4 x half> %src1.vec, i64 1
183 %src1.el1 = extractelement <2 x half> %src1.vec, i64 0
[all …]
/llvm-project-15.0.7/llvm/lib/Target/AMDGPU/
H A DAMDGPUInstrInfo.td185 // out = (src0 + src1 > 0xFFFFFFFF) ? 1 : 0
188 // out = (src1 > src0) ? 1 : 0
225 // src1 = Denominator, src2 = Numerator).
250 // src1: dst - rat offset (aka pointer) in dwords
326 SDTCisSameAs<3, 2>, // f32 src1
386 [(int_amdgcn_ldexp node:$src0, node:$src1),
387 (AMDGPUldexp_impl node:$src0, node:$src1)]>;
390 [(int_amdgcn_class node:$src0, node:$src1),
391 (AMDGPUfp_class_impl node:$src0, node:$src1)]>;
438 [(int_amdgcn_mul_u24 node:$src0, node:$src1),
[all …]
/llvm-project-15.0.7/llvm/test/CodeGen/AArch64/GlobalISel/
H A Dselect-st2.mir17 ; CHECK: %src1:fpr64 = COPY $d0
23 %src1:fpr(<8 x s8>) = COPY $d0
42 ; CHECK: %src1:fpr128 = COPY $q0
48 %src1:fpr(<16 x s8>) = COPY $q0
67 ; CHECK: %src1:fpr64 = COPY $d0
73 %src1:fpr(<4 x s16>) = COPY $d0
98 %src1:fpr(<8 x s16>) = COPY $q0
116 ; CHECK: %src1:fpr64 = COPY $d0
194 %src1:fpr(<2 x p0>) = COPY $q0
218 %src1:gpr(s64) = COPY $x0
[all …]
/llvm-project-15.0.7/llvm/test/CodeGen/Thumb2/
H A Dmve-shifts.ll10 %0 = shl <16 x i8> %src1, %src2
20 %0 = shl <8 x i16> %src1, %src2
30 %0 = shl <4 x i32> %src1, %src2
49 %0 = shl <2 x i64> %src1, %src2
61 %0 = lshr <16 x i8> %src1, %src2
72 %0 = lshr <8 x i16> %src1, %src2
308 %0 = shl <16 x i8> %src1, %s
320 %0 = shl <8 x i16> %src1, %s
332 %0 = shl <4 x i32> %src1, %s
349 %0 = shl <2 x i64> %src1, %s
[all …]
/llvm-project-15.0.7/llvm/test/CodeGen/AMDGPU/GlobalISel/
H A Dpostlegalizer-combiner-divrem.mir15 ; CHECK-NEXT: %src1:_(s32) = COPY $vgpr0
23 %src1:_(s32) = COPY $vgpr0
42 ; CHECK-NEXT: %src1:_(s32) = COPY $vgpr0
50 %src1:_(s32) = COPY $vgpr0
69 ; CHECK-NEXT: %src1:_(s32) = COPY $vgpr0
77 %src1:_(s32) = COPY $vgpr0
104 %src1:_(s32) = COPY $vgpr0
131 %src1:_(<2 x s32>) = COPY $vgpr0_vgpr1
158 %src1:_(<2 x s32>) = COPY $vgpr0_vgpr1
188 %src1:_(s32) = COPY $vgpr0
[all …]
H A Dprelegalizer-combiner-divrem.mir20 %src1:_(s32) = COPY $vgpr0
95 %src1:_(s32) = COPY $vgpr0
170 %src1:_(s32) = COPY $vgpr0
245 %src1:_(s32) = COPY $vgpr0
324 %src1:_(s32) = COPY $vgpr0
358 %src1:_(s32) = COPY $vgpr0
391 %src1:_(s32) = COPY $vgpr0
422 %src1:_(s32) = COPY $vgpr0
449 %src1:_(s32) = COPY $vgpr0
475 %src1:_(s32) = COPY $vgpr0
[all …]
H A Dorn2.ll22 %not.src1 = xor i32 %src1, -1
42 %not.src1 = xor i32 %src1, -1
65 %not.src1 = xor i32 %src1, -1
113 %not.src1 = xor i32 %src1, -1
130 %not.src1 = xor i32 %src1, -1
148 %not.src1 = xor i32 %src1, -1
169 %not.src1 = xor i64 %src1, -1
189 %not.src1 = xor i64 %src1, -1
240 %not.src1 = xor i64 %src1, -1
266 %not.src1 = xor i64 %src1, -1
[all …]
H A Dandn2.ll22 %not.src1 = xor i32 %src1, -1
42 %not.src1 = xor i32 %src1, -1
65 %not.src1 = xor i32 %src1, -1
113 %not.src1 = xor i32 %src1, -1
130 %not.src1 = xor i32 %src1, -1
148 %not.src1 = xor i32 %src1, -1
169 %not.src1 = xor i64 %src1, -1
189 %not.src1 = xor i64 %src1, -1
240 %not.src1 = xor i64 %src1, -1
266 %not.src1 = xor i64 %src1, -1
[all …]

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