Lines Matching refs:src1
17 let Constraints = "$src1 = $dst", SchedRW = [WriteShift] in {
19 def SHL8rCL : I<0xD2, MRM4r, (outs GR8 :$dst), (ins GR8 :$src1),
21 [(set GR8:$dst, (shl GR8:$src1, CL))]>;
22 def SHL16rCL : I<0xD3, MRM4r, (outs GR16:$dst), (ins GR16:$src1),
24 [(set GR16:$dst, (shl GR16:$src1, CL))]>, OpSize16;
25 def SHL32rCL : I<0xD3, MRM4r, (outs GR32:$dst), (ins GR32:$src1),
27 [(set GR32:$dst, (shl GR32:$src1, CL))]>, OpSize32;
28 def SHL64rCL : RI<0xD3, MRM4r, (outs GR64:$dst), (ins GR64:$src1),
30 [(set GR64:$dst, (shl GR64:$src1, CL))]>;
34 def SHL8ri : Ii8<0xC0, MRM4r, (outs GR8 :$dst), (ins GR8 :$src1, u8imm:$src2),
36 [(set GR8:$dst, (shl GR8:$src1, (i8 imm:$src2)))]>;
38 def SHL16ri : Ii8<0xC1, MRM4r, (outs GR16:$dst), (ins GR16:$src1, u8imm:$src2),
40 [(set GR16:$dst, (shl GR16:$src1, (i8 imm:$src2)))]>,
42 def SHL32ri : Ii8<0xC1, MRM4r, (outs GR32:$dst), (ins GR32:$src1, u8imm:$src2),
44 [(set GR32:$dst, (shl GR32:$src1, (i8 imm:$src2)))]>,
47 (ins GR64:$src1, u8imm:$src2),
49 [(set GR64:$dst, (shl GR64:$src1, (i8 imm:$src2)))]>;
55 def SHL8r1 : I<0xD0, MRM4r, (outs GR8:$dst), (ins GR8:$src1),
57 def SHL16r1 : I<0xD1, MRM4r, (outs GR16:$dst), (ins GR16:$src1),
59 def SHL32r1 : I<0xD1, MRM4r, (outs GR32:$dst), (ins GR32:$src1),
61 def SHL64r1 : RI<0xD1, MRM4r, (outs GR64:$dst), (ins GR64:$src1),
121 let Constraints = "$src1 = $dst", SchedRW = [WriteShift] in {
123 def SHR8rCL : I<0xD2, MRM5r, (outs GR8 :$dst), (ins GR8 :$src1),
125 [(set GR8:$dst, (srl GR8:$src1, CL))]>;
126 def SHR16rCL : I<0xD3, MRM5r, (outs GR16:$dst), (ins GR16:$src1),
128 [(set GR16:$dst, (srl GR16:$src1, CL))]>, OpSize16;
129 def SHR32rCL : I<0xD3, MRM5r, (outs GR32:$dst), (ins GR32:$src1),
131 [(set GR32:$dst, (srl GR32:$src1, CL))]>, OpSize32;
132 def SHR64rCL : RI<0xD3, MRM5r, (outs GR64:$dst), (ins GR64:$src1),
134 [(set GR64:$dst, (srl GR64:$src1, CL))]>;
137 def SHR8ri : Ii8<0xC0, MRM5r, (outs GR8:$dst), (ins GR8:$src1, u8imm:$src2),
139 [(set GR8:$dst, (srl GR8:$src1, (i8 imm:$src2)))]>;
140 def SHR16ri : Ii8<0xC1, MRM5r, (outs GR16:$dst), (ins GR16:$src1, u8imm:$src2),
142 [(set GR16:$dst, (srl GR16:$src1, (i8 imm:$src2)))]>,
144 def SHR32ri : Ii8<0xC1, MRM5r, (outs GR32:$dst), (ins GR32:$src1, u8imm:$src2),
146 [(set GR32:$dst, (srl GR32:$src1, (i8 imm:$src2)))]>,
148 def SHR64ri : RIi8<0xC1, MRM5r, (outs GR64:$dst), (ins GR64:$src1, u8imm:$src2),
150 [(set GR64:$dst, (srl GR64:$src1, (i8 imm:$src2)))]>;
153 def SHR8r1 : I<0xD0, MRM5r, (outs GR8:$dst), (ins GR8:$src1),
155 [(set GR8:$dst, (srl GR8:$src1, (i8 1)))]>;
156 def SHR16r1 : I<0xD1, MRM5r, (outs GR16:$dst), (ins GR16:$src1),
158 [(set GR16:$dst, (srl GR16:$src1, (i8 1)))]>, OpSize16;
159 def SHR32r1 : I<0xD1, MRM5r, (outs GR32:$dst), (ins GR32:$src1),
161 [(set GR32:$dst, (srl GR32:$src1, (i8 1)))]>, OpSize32;
162 def SHR64r1 : RI<0xD1, MRM5r, (outs GR64:$dst), (ins GR64:$src1),
164 [(set GR64:$dst, (srl GR64:$src1, (i8 1)))]>;
221 let Constraints = "$src1 = $dst", SchedRW = [WriteShift] in {
223 def SAR8rCL : I<0xD2, MRM7r, (outs GR8 :$dst), (ins GR8 :$src1),
225 [(set GR8:$dst, (sra GR8:$src1, CL))]>;
226 def SAR16rCL : I<0xD3, MRM7r, (outs GR16:$dst), (ins GR16:$src1),
228 [(set GR16:$dst, (sra GR16:$src1, CL))]>,
230 def SAR32rCL : I<0xD3, MRM7r, (outs GR32:$dst), (ins GR32:$src1),
232 [(set GR32:$dst, (sra GR32:$src1, CL))]>,
234 def SAR64rCL : RI<0xD3, MRM7r, (outs GR64:$dst), (ins GR64:$src1),
236 [(set GR64:$dst, (sra GR64:$src1, CL))]>;
239 def SAR8ri : Ii8<0xC0, MRM7r, (outs GR8 :$dst), (ins GR8 :$src1, u8imm:$src2),
241 [(set GR8:$dst, (sra GR8:$src1, (i8 imm:$src2)))]>;
242 def SAR16ri : Ii8<0xC1, MRM7r, (outs GR16:$dst), (ins GR16:$src1, u8imm:$src2),
244 [(set GR16:$dst, (sra GR16:$src1, (i8 imm:$src2)))]>,
246 def SAR32ri : Ii8<0xC1, MRM7r, (outs GR32:$dst), (ins GR32:$src1, u8imm:$src2),
248 [(set GR32:$dst, (sra GR32:$src1, (i8 imm:$src2)))]>,
251 (ins GR64:$src1, u8imm:$src2),
253 [(set GR64:$dst, (sra GR64:$src1, (i8 imm:$src2)))]>;
256 def SAR8r1 : I<0xD0, MRM7r, (outs GR8 :$dst), (ins GR8 :$src1),
258 [(set GR8:$dst, (sra GR8:$src1, (i8 1)))]>;
259 def SAR16r1 : I<0xD1, MRM7r, (outs GR16:$dst), (ins GR16:$src1),
261 [(set GR16:$dst, (sra GR16:$src1, (i8 1)))]>, OpSize16;
262 def SAR32r1 : I<0xD1, MRM7r, (outs GR32:$dst), (ins GR32:$src1),
264 [(set GR32:$dst, (sra GR32:$src1, (i8 1)))]>, OpSize32;
265 def SAR64r1 : RI<0xD1, MRM7r, (outs GR64:$dst), (ins GR64:$src1),
267 [(set GR64:$dst, (sra GR64:$src1, (i8 1)))]>;
329 let Constraints = "$src1 = $dst", SchedRW = [WriteRotate] in {
332 def RCL8rCL : I<0xD2, MRM2r, (outs GR8:$dst), (ins GR8:$src1),
334 def RCL16rCL : I<0xD3, MRM2r, (outs GR16:$dst), (ins GR16:$src1),
336 def RCL32rCL : I<0xD3, MRM2r, (outs GR32:$dst), (ins GR32:$src1),
338 def RCL64rCL : RI<0xD3, MRM2r, (outs GR64:$dst), (ins GR64:$src1),
343 def RCL8r1 : I<0xD0, MRM2r, (outs GR8:$dst), (ins GR8:$src1),
345 def RCL8ri : Ii8<0xC0, MRM2r, (outs GR8:$dst), (ins GR8:$src1, u8imm:$cnt),
347 def RCL16r1 : I<0xD1, MRM2r, (outs GR16:$dst), (ins GR16:$src1),
349 def RCL16ri : Ii8<0xC1, MRM2r, (outs GR16:$dst), (ins GR16:$src1, u8imm:$cnt),
351 def RCL32r1 : I<0xD1, MRM2r, (outs GR32:$dst), (ins GR32:$src1),
353 def RCL32ri : Ii8<0xC1, MRM2r, (outs GR32:$dst), (ins GR32:$src1, u8imm:$cnt),
355 def RCL64r1 : RI<0xD1, MRM2r, (outs GR64:$dst), (ins GR64:$src1),
357 def RCL64ri : RIi8<0xC1, MRM2r, (outs GR64:$dst), (ins GR64:$src1, u8imm:$cnt),
362 def RCR8rCL : I<0xD2, MRM3r, (outs GR8:$dst), (ins GR8:$src1),
364 def RCR16rCL : I<0xD3, MRM3r, (outs GR16:$dst), (ins GR16:$src1),
366 def RCR32rCL : I<0xD3, MRM3r, (outs GR32:$dst), (ins GR32:$src1),
368 def RCR64rCL : RI<0xD3, MRM3r, (outs GR64:$dst), (ins GR64:$src1),
373 def RCR8r1 : I<0xD0, MRM3r, (outs GR8:$dst), (ins GR8:$src1),
375 def RCR8ri : Ii8<0xC0, MRM3r, (outs GR8:$dst), (ins GR8:$src1, u8imm:$cnt),
377 def RCR16r1 : I<0xD1, MRM3r, (outs GR16:$dst), (ins GR16:$src1),
379 def RCR16ri : Ii8<0xC1, MRM3r, (outs GR16:$dst), (ins GR16:$src1, u8imm:$cnt),
381 def RCR32r1 : I<0xD1, MRM3r, (outs GR32:$dst), (ins GR32:$src1),
383 def RCR32ri : Ii8<0xC1, MRM3r, (outs GR32:$dst), (ins GR32:$src1, u8imm:$cnt),
385 def RCR64r1 : RI<0xD1, MRM3r, (outs GR64:$dst), (ins GR64:$src1),
387 def RCR64ri : RIi8<0xC1, MRM3r, (outs GR64:$dst), (ins GR64:$src1, u8imm:$cnt),
456 let Constraints = "$src1 = $dst", SchedRW = [WriteRotate] in {
459 def ROL8rCL : I<0xD2, MRM0r, (outs GR8 :$dst), (ins GR8 :$src1),
461 [(set GR8:$dst, (rotl GR8:$src1, CL))]>;
462 def ROL16rCL : I<0xD3, MRM0r, (outs GR16:$dst), (ins GR16:$src1),
464 [(set GR16:$dst, (rotl GR16:$src1, CL))]>, OpSize16;
465 def ROL32rCL : I<0xD3, MRM0r, (outs GR32:$dst), (ins GR32:$src1),
467 [(set GR32:$dst, (rotl GR32:$src1, CL))]>, OpSize32;
468 def ROL64rCL : RI<0xD3, MRM0r, (outs GR64:$dst), (ins GR64:$src1),
470 [(set GR64:$dst, (rotl GR64:$src1, CL))]>;
473 def ROL8ri : Ii8<0xC0, MRM0r, (outs GR8 :$dst), (ins GR8 :$src1, u8imm:$src2),
475 [(set GR8:$dst, (rotl GR8:$src1, (i8 imm:$src2)))]>;
476 def ROL16ri : Ii8<0xC1, MRM0r, (outs GR16:$dst), (ins GR16:$src1, u8imm:$src2),
478 [(set GR16:$dst, (rotl GR16:$src1, (i8 imm:$src2)))]>,
480 def ROL32ri : Ii8<0xC1, MRM0r, (outs GR32:$dst), (ins GR32:$src1, u8imm:$src2),
482 [(set GR32:$dst, (rotl GR32:$src1, (i8 imm:$src2)))]>,
485 (ins GR64:$src1, u8imm:$src2),
487 [(set GR64:$dst, (rotl GR64:$src1, (i8 imm:$src2)))]>;
490 def ROL8r1 : I<0xD0, MRM0r, (outs GR8 :$dst), (ins GR8 :$src1),
492 [(set GR8:$dst, (rotl GR8:$src1, (i8 1)))]>;
493 def ROL16r1 : I<0xD1, MRM0r, (outs GR16:$dst), (ins GR16:$src1),
495 [(set GR16:$dst, (rotl GR16:$src1, (i8 1)))]>, OpSize16;
496 def ROL32r1 : I<0xD1, MRM0r, (outs GR32:$dst), (ins GR32:$src1),
498 [(set GR32:$dst, (rotl GR32:$src1, (i8 1)))]>, OpSize32;
499 def ROL64r1 : RI<0xD1, MRM0r, (outs GR64:$dst), (ins GR64:$src1),
501 [(set GR64:$dst, (rotl GR64:$src1, (i8 1)))]>;
521 def ROL8mi : Ii8<0xC0, MRM0m, (outs), (ins i8mem :$dst, u8imm:$src1),
522 "rol{b}\t{$src1, $dst|$dst, $src1}",
523 [(store (rotl (loadi8 addr:$dst), (i8 imm:$src1)), addr:$dst)]>;
524 def ROL16mi : Ii8<0xC1, MRM0m, (outs), (ins i16mem:$dst, u8imm:$src1),
525 "rol{w}\t{$src1, $dst|$dst, $src1}",
526 [(store (rotl (loadi16 addr:$dst), (i8 imm:$src1)), addr:$dst)]>,
528 def ROL32mi : Ii8<0xC1, MRM0m, (outs), (ins i32mem:$dst, u8imm:$src1),
529 "rol{l}\t{$src1, $dst|$dst, $src1}",
530 [(store (rotl (loadi32 addr:$dst), (i8 imm:$src1)), addr:$dst)]>,
532 def ROL64mi : RIi8<0xC1, MRM0m, (outs), (ins i64mem:$dst, u8imm:$src1),
533 "rol{q}\t{$src1, $dst|$dst, $src1}",
534 [(store (rotl (loadi64 addr:$dst), (i8 imm:$src1)), addr:$dst)]>,
555 let Constraints = "$src1 = $dst", SchedRW = [WriteRotate] in {
557 def ROR8rCL : I<0xD2, MRM1r, (outs GR8 :$dst), (ins GR8 :$src1),
559 [(set GR8:$dst, (rotr GR8:$src1, CL))]>;
560 def ROR16rCL : I<0xD3, MRM1r, (outs GR16:$dst), (ins GR16:$src1),
562 [(set GR16:$dst, (rotr GR16:$src1, CL))]>, OpSize16;
563 def ROR32rCL : I<0xD3, MRM1r, (outs GR32:$dst), (ins GR32:$src1),
565 [(set GR32:$dst, (rotr GR32:$src1, CL))]>, OpSize32;
566 def ROR64rCL : RI<0xD3, MRM1r, (outs GR64:$dst), (ins GR64:$src1),
568 [(set GR64:$dst, (rotr GR64:$src1, CL))]>;
571 def ROR8ri : Ii8<0xC0, MRM1r, (outs GR8 :$dst), (ins GR8 :$src1, u8imm:$src2),
573 [(set GR8:$dst, (rotr GR8:$src1, (i8 imm:$src2)))]>;
574 def ROR16ri : Ii8<0xC1, MRM1r, (outs GR16:$dst), (ins GR16:$src1, u8imm:$src2),
576 [(set GR16:$dst, (rotr GR16:$src1, (i8 imm:$src2)))]>,
578 def ROR32ri : Ii8<0xC1, MRM1r, (outs GR32:$dst), (ins GR32:$src1, u8imm:$src2),
580 [(set GR32:$dst, (rotr GR32:$src1, (i8 imm:$src2)))]>,
583 (ins GR64:$src1, u8imm:$src2),
585 [(set GR64:$dst, (rotr GR64:$src1, (i8 imm:$src2)))]>;
588 def ROR8r1 : I<0xD0, MRM1r, (outs GR8 :$dst), (ins GR8 :$src1),
590 [(set GR8:$dst, (rotr GR8:$src1, (i8 1)))]>;
591 def ROR16r1 : I<0xD1, MRM1r, (outs GR16:$dst), (ins GR16:$src1),
593 [(set GR16:$dst, (rotr GR16:$src1, (i8 1)))]>, OpSize16;
594 def ROR32r1 : I<0xD1, MRM1r, (outs GR32:$dst), (ins GR32:$src1),
596 [(set GR32:$dst, (rotr GR32:$src1, (i8 1)))]>, OpSize32;
597 def ROR64r1 : RI<0xD1, MRM1r, (outs GR64:$dst), (ins GR64:$src1),
599 [(set GR64:$dst, (rotr GR64:$src1, (i8 1)))]>;
658 let Constraints = "$src1 = $dst" in {
662 (ins GR16:$src1, GR16:$src2),
664 [(set GR16:$dst, (X86fshl GR16:$src1, GR16:$src2, CL))]>,
667 (ins GR16:$src1, GR16:$src2),
669 [(set GR16:$dst, (X86fshr GR16:$src2, GR16:$src1, CL))]>,
672 (ins GR32:$src1, GR32:$src2),
674 [(set GR32:$dst, (fshl GR32:$src1, GR32:$src2, CL))]>,
677 (ins GR32:$src1, GR32:$src2),
679 [(set GR32:$dst, (fshr GR32:$src2, GR32:$src1, CL))]>,
682 (ins GR64:$src1, GR64:$src2),
684 [(set GR64:$dst, (fshl GR64:$src1, GR64:$src2, CL))]>,
687 (ins GR64:$src1, GR64:$src2),
689 [(set GR64:$dst, (fshr GR64:$src2, GR64:$src1, CL))]>,
696 (ins GR16:$src1, GR16:$src2, u8imm:$src3),
698 [(set GR16:$dst, (X86fshl GR16:$src1, GR16:$src2,
703 (ins GR16:$src1, GR16:$src2, u8imm:$src3),
705 [(set GR16:$dst, (X86fshr GR16:$src2, GR16:$src1,
710 (ins GR32:$src1, GR32:$src2, u8imm:$src3),
712 [(set GR32:$dst, (fshl GR32:$src1, GR32:$src2,
717 (ins GR32:$src1, GR32:$src2, u8imm:$src3),
719 [(set GR32:$dst, (fshr GR32:$src2, GR32:$src1,
724 (ins GR64:$src1, GR64:$src2, u8imm:$src3),
726 [(set GR64:$dst, (fshl GR64:$src1, GR64:$src2,
731 (ins GR64:$src1, GR64:$src2, u8imm:$src3),
733 [(set GR64:$dst, (fshr GR64:$src2, GR64:$src1,
812 def : Pat<(rotl GR8:$src1, (i8 7)), (ROR8r1 GR8:$src1)>;
813 def : Pat<(rotl GR16:$src1, (i8 15)), (ROR16r1 GR16:$src1)>;
814 def : Pat<(rotl GR32:$src1, (i8 31)), (ROR32r1 GR32:$src1)>;
815 def : Pat<(rotl GR64:$src1, (i8 63)), (ROR64r1 GR64:$src1)>;
816 def : Pat<(rotr GR8:$src1, (i8 7)), (ROL8r1 GR8:$src1)>;
817 def : Pat<(rotr GR16:$src1, (i8 15)), (ROL16r1 GR16:$src1)>;
818 def : Pat<(rotr GR32:$src1, (i8 31)), (ROL32r1 GR32:$src1)>;
819 def : Pat<(rotr GR64:$src1, (i8 63)), (ROL64r1 GR64:$src1)>;
845 Constraints = "$src1 = $dst" in {
847 (ins GR32:$src1, u8imm:$shamt), "",
848 [(set GR32:$dst, (rotl GR32:$src1, (i8 imm:$shamt)))]>;
850 (ins GR64:$src1, u8imm:$shamt), "",
851 [(set GR64:$dst, (rotl GR64:$src1, (i8 imm:$shamt)))]>;
854 (ins GR32:$src1, u8imm:$shamt), "",
855 [(set GR32:$dst, (rotr GR32:$src1, (i8 imm:$shamt)))]>;
857 (ins GR64:$src1, u8imm:$shamt), "",
858 [(set GR64:$dst, (rotr GR64:$src1, (i8 imm:$shamt)))]>;
875 def ri : Ii8<0xF0, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, u8imm:$src2),
876 !strconcat(asm, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
880 (ins x86memop:$src1, u8imm:$src2),
881 !strconcat(asm, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
888 def rr : I<0xF7, MRMSrcReg4VOp3, (outs RC:$dst), (ins RC:$src1, RC:$src2),
889 !strconcat(asm, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>,
893 (outs RC:$dst), (ins x86memop:$src1, RC:$src2),
894 !strconcat(asm, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>,
896 // x86memop:$src1
951 def : Pat<(sra GR32:$src1, GR8:$src2),
952 (SARX32rr GR32:$src1,
955 def : Pat<(sra GR64:$src1, GR8:$src2),
956 (SARX64rr GR64:$src1,
960 def : Pat<(srl GR32:$src1, GR8:$src2),
961 (SHRX32rr GR32:$src1,
964 def : Pat<(srl GR64:$src1, GR8:$src2),
965 (SHRX64rr GR64:$src1,
969 def : Pat<(shl GR32:$src1, GR8:$src2),
970 (SHLX32rr GR32:$src1,
973 def : Pat<(shl GR64:$src1, GR8:$src2),
974 (SHLX64rr GR64:$src1,
989 def : Pat<(sra (loadi32 addr:$src1), GR8:$src2),
990 (SARX32rm addr:$src1,
993 def : Pat<(sra (loadi64 addr:$src1), GR8:$src2),
994 (SARX64rm addr:$src1,
998 def : Pat<(srl (loadi32 addr:$src1), GR8:$src2),
999 (SHRX32rm addr:$src1,
1002 def : Pat<(srl (loadi64 addr:$src1), GR8:$src2),
1003 (SHRX64rm addr:$src1,
1007 def : Pat<(shl (loadi32 addr:$src1), GR8:$src2),
1008 (SHLX32rm addr:$src1,
1011 def : Pat<(shl (loadi64 addr:$src1), GR8:$src2),
1012 (SHLX64rm addr:$src1,
1017 def : Pat<(rotl GR8:$src1, (i8 relocImm:$src2)),
1018 (ROL8ri GR8:$src1, relocImm:$src2)>;
1019 def : Pat<(rotl GR16:$src1, (i8 relocImm:$src2)),
1020 (ROL16ri GR16:$src1, relocImm:$src2)>;
1021 def : Pat<(rotl GR32:$src1, (i8 relocImm:$src2)),
1022 (ROL32ri GR32:$src1, relocImm:$src2)>;
1023 def : Pat<(rotl GR64:$src1, (i8 relocImm:$src2)),
1024 (ROL64ri GR64:$src1, relocImm:$src2)>;
1026 def : Pat<(rotr GR8:$src1, (i8 relocImm:$src2)),
1027 (ROR8ri GR8:$src1, relocImm:$src2)>;
1028 def : Pat<(rotr GR16:$src1, (i8 relocImm:$src2)),
1029 (ROR16ri GR16:$src1, relocImm:$src2)>;
1030 def : Pat<(rotr GR32:$src1, (i8 relocImm:$src2)),
1031 (ROR32ri GR32:$src1, relocImm:$src2)>;
1032 def : Pat<(rotr GR64:$src1, (i8 relocImm:$src2)),
1033 (ROR64ri GR64:$src1, relocImm:$src2)>;