Lines Matching refs:src1

185 // out = (src0 + src1 > 0xFFFFFFFF) ? 1 : 0
188 // out = (src1 > src0) ? 1 : 0
225 // src1 = Denominator, src2 = Numerator).
230 // Special case divide fixup and flags(src0 = Quotient, src1 =
250 // src1: dst - rat offset (aka pointer) in dwords
326 SDTCisSameAs<3, 2>, // f32 src1
385 def AMDGPUldexp : PatFrags<(ops node:$src0, node:$src1),
386 [(int_amdgcn_ldexp node:$src0, node:$src1),
387 (AMDGPUldexp_impl node:$src0, node:$src1)]>;
389 def AMDGPUfp_class : PatFrags<(ops node:$src0, node:$src1),
390 [(int_amdgcn_class node:$src0, node:$src1),
391 (AMDGPUfp_class_impl node:$src0, node:$src1)]>;
393 def AMDGPUfmed3 : PatFrags<(ops node:$src0, node:$src1, node:$src2),
394 [(int_amdgcn_fmed3 node:$src0, node:$src1, node:$src2),
395 (AMDGPUfmed3_impl node:$src0, node:$src1, node:$src2)]>;
397 def AMDGPUdiv_fixup : PatFrags<(ops node:$src0, node:$src1, node:$src2),
398 [(int_amdgcn_div_fixup node:$src0, node:$src1, node:$src2),
399 (AMDGPUdiv_fixup_impl node:$src0, node:$src1, node:$src2)]>;
413 def AMDGPUpkrtz_f16_f32 : PatFrags<(ops node:$src0, node:$src1),
414 [(int_amdgcn_cvt_pkrtz node:$src0, node:$src1),
415 (AMDGPUpkrtz_f16_f32_impl node:$src0, node:$src1)]>;
417 def AMDGPUpknorm_i16_f32 : PatFrags<(ops node:$src0, node:$src1),
418 [(int_amdgcn_cvt_pknorm_i16 node:$src0, node:$src1),
419 (AMDGPUpknorm_i16_f32_impl node:$src0, node:$src1)]>;
421 def AMDGPUpknorm_u16_f32 : PatFrags<(ops node:$src0, node:$src1),
422 [(int_amdgcn_cvt_pknorm_u16 node:$src0, node:$src1),
423 (AMDGPUpknorm_u16_f32_impl node:$src0, node:$src1)]>;
425 def AMDGPUpk_i16_i32 : PatFrags<(ops node:$src0, node:$src1),
426 [(int_amdgcn_cvt_pk_i16 node:$src0, node:$src1),
427 (AMDGPUpk_i16_i32_impl node:$src0, node:$src1)]>;
429 def AMDGPUpk_u16_u32 : PatFrags<(ops node:$src0, node:$src1),
430 [(int_amdgcn_cvt_pk_u16 node:$src0, node:$src1),
431 (AMDGPUpk_u16_u32_impl node:$src0, node:$src1)]>;
433 def AMDGPUfmad_ftz : PatFrags<(ops node:$src0, node:$src1, node:$src2),
434 [(int_amdgcn_fmad_ftz node:$src0, node:$src1, node:$src2),
435 (AMDGPUfmad_ftz_impl node:$src0, node:$src1, node:$src2)]>;
437 def AMDGPUmul_u24 : PatFrags<(ops node:$src0, node:$src1),
438 [(int_amdgcn_mul_u24 node:$src0, node:$src1),
439 (AMDGPUmul_u24_impl node:$src0, node:$src1)]>;
441 def AMDGPUmul_i24 : PatFrags<(ops node:$src0, node:$src1),
442 [(int_amdgcn_mul_i24 node:$src0, node:$src1),
443 (AMDGPUmul_i24_impl node:$src0, node:$src1)]>;
445 def AMDGPUmulhi_u24 : PatFrags<(ops node:$src0, node:$src1),
446 [(int_amdgcn_mulhi_u24 node:$src0, node:$src1),
447 (AMDGPUmulhi_u24_impl node:$src0, node:$src1)]>;
449 def AMDGPUmulhi_i24 : PatFrags<(ops node:$src0, node:$src1),
450 [(int_amdgcn_mulhi_i24 node:$src0, node:$src1),
451 (AMDGPUmulhi_i24_impl node:$src0, node:$src1)]>;
453 def AMDGPUbfe_i32 : PatFrags<(ops node:$src0, node:$src1, node:$src2),
454 [(int_amdgcn_sbfe node:$src0, node:$src1, node:$src2),
455 (AMDGPUbfe_i32_impl node:$src0, node:$src1, node:$src2)]>;
457 def AMDGPUbfe_u32 : PatFrags<(ops node:$src0, node:$src1, node:$src2),
458 [(int_amdgcn_ubfe node:$src0, node:$src1, node:$src2),
459 (AMDGPUbfe_u32_impl node:$src0, node:$src1, node:$src2)]>;
461 def AMDGPUfmul_legacy : PatFrags<(ops node:$src0, node:$src1),
462 [(int_amdgcn_fmul_legacy node:$src0, node:$src1),
463 (AMDGPUfmul_legacy_impl node:$src0, node:$src1)]>;
465 def AMDGPUfdot2 : PatFrags<(ops node:$src0, node:$src1, node:$src2, node:$clamp),
466 [(int_amdgcn_fdot2 node:$src0, node:$src1, node:$src2, node:$clamp),
467 (AMDGPUfdot2_impl node:$src0, node:$src1, node:$src2, node:$clamp)]>;
469 def AMDGPUdiv_fmas : PatFrags<(ops node:$src0, node:$src1, node:$src2, node:$vcc),
470 [(int_amdgcn_div_fmas node:$src0, node:$src1, node:$src2, node:$vcc),
471 (AMDGPUdiv_fmas_impl node:$src0, node:$src1, node:$src2, node:$vcc)]>;
473 def AMDGPUperm : PatFrags<(ops node:$src0, node:$src1, node:$src2),
474 [(int_amdgcn_perm node:$src0, node:$src1, node:$src2),
475 (AMDGPUperm_impl node:$src0, node:$src1, node:$src2)]>;