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/llvm-project-15.0.7/llvm/lib/Target/Sparc/
H A DSparcInstrAliases.td373 // not rd -> xnor rd, %g0, rd
379 // neg rd -> sub %g0, rd, rd
385 // inc rd -> add rd, 1, rd
388 // inc simm13, rd -> add rd, simm13, rd
391 // inccc rd -> addcc rd, 1, rd
394 // inccc simm13, rd -> addcc rd, simm13, rd
397 // dec rd -> sub rd, 1, rd
400 // dec simm13, rd -> sub rd, simm13, rd
403 // deccc rd -> subcc rd, 1, rd
442 // mov specialreg, rd -> rd specialreg, rd
[all …]
H A DSparcInstrVIS.td20 (outs RC:$rd), (ins RC:$rs1, RC:$rs2),
30 let rd = 0, rs1 = 0, rs2 = 0 in
38 (outs RC:$rd), (ins RC:$rs1),
39 !strconcat(OpcStr, " $rs1, $rd"), []>;
45 (outs RC:$rd), (ins RC:$rs2),
46 !strconcat(OpcStr, " $rs2, $rd"), []>;
48 // For VIS Instructions with only rd operand.
49 let Constraints = "$rd = $f", rs1 = 0, rs2 = 0 in
52 (outs RC:$rd), (ins RC:$f),
53 !strconcat(OpcStr, " $rd"), []>;
[all …]
H A DSparcInstrInfo.td593 let rd = 0 in {
603 let rd = 0 in {
609 let rd = 1 in {
673 let rd = 0 in {
1097 "rd $rs1, $rd", []>;
1104 "rd %psr, $rd", []>;
1109 "rd %wim, $rd", []>;
1114 "rd %tbr, $rd", []>;
1122 "rd %pc, $rd", []>;
1169 let rd = 0 in
[all …]
H A DSparcInstr64Bit.td168 [(set i64:$rd,
327 [(set i32:$rd,
332 [(set i32:$rd,
340 [(set f32:$rd,
442 "fxtos $rs2, $rd",
446 "fxtod $rs2, $rd",
451 "fxtoq $rs2, $rd",
456 "fstox $rs2, $rd",
460 "fdtox $rs2, $rd",
465 "fqtox $rs2, $rd",
[all …]
/llvm-project-15.0.7/clang/test/Analysis/
H A Dcfg-openmp.cpp25 int x, cond, fp, rd, lin, step, map; in target_s_has_device_addr() local
51 int x, cond, fp, rd, map; in target_t_l_has_device_addr() local
74 int x, cond, fp, rd, map; in target_p_l_has_device_addr() local
134 int x, cond, fp, rd, lin, step, map; in xxx() local
297 int x, cond, fp, rd, lin, step, map; in dpf() local
319 int x, cond, fp, rd, lin, step, map; in dpfs() local
341 int x, cond, fp, rd, lin, step, map; in ds() local
358 int x, cond, fp, rd, lin, step, map; in for_fn() local
927 int x, cond, fp, rd, map; in targetteamsloop() local
951 int x, cond, fp, rd; in parallelloop() local
[all …]
/llvm-project-15.0.7/llvm/test/CodeGen/NVPTX/
H A Dload-store.ll6 ; CHECK: ld.u8 %rs{{[0-9]+}}, [%rd{{[0-9]+}}]
9 ; CHECK: st.u8 [%rd{{[0-9]+}}], %rs{{[0-9]+}}
12 ; CHECK: ld.u16 %rs{{[0-9]+}}, [%rd{{[0-9]+}}]
18 ; CHECK: ld.u32 %r{{[0-9]+}}, [%rd{{[0-9]+}}]
21 ; CHECK: st.u32 [%rd{{[0-9]+}}], %r{{[0-9]+}}
24 ; CHECK: ld.u64 %rd{{[0-9]+}}, [%rd{{[0-9]+}}]
27 ; CHECK: st.u64 [%rd{{[0-9]+}}], %rd{{[0-9]+}}
53 ; CHECK: ld.volatile.u64 %rd{{[0-9]+}}, [%rd{{[0-9]+}}]
56 ; CHECK: st.volatile.u64 [%rd{{[0-9]+}}], %rd{{[0-9]+}}
82 ; CHECK: ld.volatile.u64 %rd{{[0-9]+}}, [%rd{{[0-9]+}}]
[all …]
H A Dmbarrier.ll31 ; CHECK_PTX64: mbarrier.inval.b64 [%rd{{[0-1]+}}];
50 ; CHECK_PTX64: mbarrier.arrive.b64 %rd{{[0-9]+}}, [%rd{{[0-9]+}}];
58 ; CHECK_PTX64: mbarrier.arrive.shared.b64 %rd{{[0-9]+}}, [%rd{{[0-9]+}}];
69 ; CHECK_PTX64: mbarrier.arrive.noComplete.b64 %rd{{[0-9]+}}, [%rd{{[0-9]+}}], %r{{[0-9]+}};
77 ; CHECK_PTX64: mbarrier.arrive.noComplete.shared.b64 %rd{{[0-9]+}}, [%rd{{[0-9]+}}], %r{{[0-9]+}};
88 ; CHECK_PTX64: mbarrier.arrive_drop.b64 %rd{{[0-9]+}}, [%rd{{[0-9]+}}];
96 ; CHECK_PTX64: mbarrier.arrive_drop.shared.b64 %rd{{[0-9]+}}, [%rd{{[0-9]+}}];
107 ; CHECK_PTX64: mbarrier.arrive_drop.noComplete.b64 %rd{{[0-9]+}}, [%rd{{[0-9]+}}], %r{{[0-9]+}};
115 ; CHECK_PTX64: mbarrier.arrive_drop.noComplete.shared.b64 %rd{{[0-9]+}}, [%rd{{[0-9]+}}], %r{{[0-9]…
126 ; CHECK_PTX64: mbarrier.test_wait.b64 %p{{[0-9]+}}, [%rd{{[0-9]+}}], %rd{{[0-9]+}};
[all …]
H A Di128-param.ll8 ; CHECK-DAG: ld.param.v2.u64 {%[[REG0:rd[0-9]+]], %[[REG1:rd[0-9]+]]}, [callee_param_0];
9 ; CHECK-DAG: ld.param.v2.u64 {%[[REG2:rd[0-9]+]], %[[REG3:rd[0-9]+]]}, [callee_param_1];
11 ; CHECK: mul.lo.s64 %[[REG4:rd[0-9]+]], %[[REG0]], %[[REG3]];
12 ; CHECK-NEXT: mul.hi.u64 %[[REG5:rd[0-9]+]], %[[REG0]], %[[REG2]];
13 ; CHECK-NEXT: add.s64 %[[REG6:rd[0-9]+]], %[[REG5]], %[[REG4]];
14 ; CHECK-NEXT: mul.lo.s64 %[[REG7:rd[0-9]+]], %[[REG1]], %[[REG2]];
15 ; CHECK-NEXT: add.s64 %[[REG8:rd[0-9]+]], %[[REG6]], %[[REG7]];
28 ; CHECK-DAG: ld.param.v2.u64 {%[[REG0:rd[0-9]+]], %[[REG1:rd[0-9]+]]}, [caller_kernel_param_0];
29 ; CHECK-DAG: ld.param.v2.u64 {%[[REG2:rd[0-9]+]], %[[REG3:rd[0-9]+]]}, [caller_kernel_param_1];
47 ; CHECK-DAG: ld.param.v2.u64 {%[[REG0:rd[0-9]+]], %[[REG1:rd[0-9]+]]}, [caller_func_param_0]
[all …]
H A Darithmetic-int.ll14 ; CHECK: add.s64 %rd{{[0-9]+}}, %rd{{[0-9]+}}, %rd{{[0-9]+}}
21 ; CHECK: sub.s64 %rd{{[0-9]+}}, %rd{{[0-9]+}}, %rd{{[0-9]+}}
28 ; CHECK: mul.lo.s64 %rd{{[0-9]+}}, %rd{{[0-9]+}}, %rd{{[0-9]+}}
59 ; CHECK: div.s64 %rd{{[0-9]+}}, %rd{{[0-9]+}}, %rd{{[0-9]+}}
66 ; CHECK: div.u64 %rd{{[0-9]+}}, %rd{{[0-9]+}}, %rd{{[0-9]+}}
73 ; CHECK: rem.s64 %rd{{[0-9]+}}, %rd{{[0-9]+}}, %rd{{[0-9]+}}
80 ; CHECK: rem.u64 %rd{{[0-9]+}}, %rd{{[0-9]+}}, %rd{{[0-9]+}}
87 ; CHECK: and.b64 %rd{{[0-9]+}}, %rd{{[0-9]+}}, %rd{{[0-9]+}}
94 ; CHECK: or.b64 %rd{{[0-9]+}}, %rd{{[0-9]+}}, %rd{{[0-9]+}}
101 ; CHECK: xor.b64 %rd{{[0-9]+}}, %rd{{[0-9]+}}, %rd{{[0-9]+}}
[all …]
H A Dst-addrspace.ll12 ; G64: st.global.u8 [%rd{{[0-9]+}}], %rs{{[0-9]+}}
20 ; LS64: st.shared.u8 [%rd{{[0-9]+}}], %rs{{[0-9]+}}
28 ; LS64: st.local.u8 [%rd{{[0-9]+}}], %rs{{[0-9]+}}
38 ; G64: st.global.u16 [%rd{{[0-9]+}}], %rs{{[0-9]+}}
54 ; LS64: st.local.u16 [%rd{{[0-9]+}}], %rs{{[0-9]+}}
64 ; G64: st.global.u32 [%rd{{[0-9]+}}], %r{{[0-9]+}}
80 ; LS64: st.local.u32 [%rd{{[0-9]+}}], %r{{[0-9]+}}
89 ; G32: st.global.u64 [%r{{[0-9]+}}], %rd{{[0-9]+}}
90 ; G64: st.global.u64 [%rd{{[0-9]+}}], %rd{{[0-9]+}}
98 ; LS64: st.shared.u64 [%rd{{[0-9]+}}], %rd{{[0-9]+}}
[all …]
H A Dld-addrspace.ll13 ; G64: ld.global.u8 %{{.*}}, [%rd{{[0-9]+}}]
21 ; LS64: ld.shared.u8 %{{.*}}, [%rd{{[0-9]+}}]
29 ; LS64: ld.local.u8 %{{.*}}, [%rd{{[0-9]+}}]
39 ; G64: ld.global.u16 %{{.*}}, [%rd{{[0-9]+}}]
47 ; LS64: ld.shared.u16 %{{.*}}, [%rd{{[0-9]+}}]
55 ; LS64: ld.local.u16 %{{.*}}, [%rd{{[0-9]+}}]
65 ; G64: ld.global.u32 %{{.*}}, [%rd{{[0-9]+}}]
81 ; LS64: ld.local.u32 %{{.*}}, [%rd{{[0-9]+}}]
91 ; G64: ld.global.u64 %{{.*}}, [%rd{{[0-9]+}}]
107 ; LS64: ld.local.u64 %{{.*}}, [%rd{{[0-9]+}}]
[all …]
H A Dlower-aggr-copies.ll41 ; PTX: st.u8 [%rd{{[0-9]+}}], %rs[[REG]]
42 ; PTX: add.s64 %rd[[COUNTER:[0-9]+]], %rd{{[0-9]+}}, 1
43 ; PTX: setp.lt.u64 %p[[PRED:[0-9]+]], %rd[[COUNTER]], %rd
76 ; PTX: add.s64 %rd[[COUNTER:[0-9]+]], %rd{{[0-9]+}}, 1
77 ; PTX: setp.lt.u64 %p[[PRED:[0-9]+]], %rd[[COUNTER]], %rd
135 ; PTX: add.s64 %rd[[COUNTER:[0-9]+]], %rd{{[0-9]+}}, 1
136 ; PTX: setp.lt.u64 %p[[PRED:[0-9]+]], %rd[[COUNTER]], %rd
166 ; PTX: ld.param.u64 %rd[[N:[0-9]+]]
168 ; PTX-DAG: setp.ge.u64 %p[[SRC_GT_THAN_DST:[0-9]+]], %rd{{[0-9]+}}, %rd{{[0-9]+}}
172 ; PTX: add.s64 %rd{{[0-9]}}, %rd{{[0-9]}}, -1
[all …]
H A Di128-retval.ll6 ; CHECK: ld.param.v2.u64 {%[[REG0:rd[0-9]+]], %[[REG1:rd[0-9]+]]}, [callee_param_0];
14 ; CHECK-DAG: ld.param.v2.u64 {%[[REG0:rd[0-9]+]], %[[REG1:rd[0-9]+]]}, [caller_param_0];
15 ; CHECK-DAG: ld.param.u64 %[[OUT:rd[0-9]+]], [caller_param_1];
20 ; CHECK: ld.param.v2.b64 {%[[REG2:rd[0-9]+]], %[[REG3:rd[0-9]+]]}, [retval0+0];
/llvm-project-15.0.7/llvm/lib/Target/CSKY/
H A DCSKYInstrInfo16Instr.td622 def : CompressPat<(AND32 sGPR:$rd, sGPR:$rd, sGPR:$rs2),
624 def : CompressPat<(AND32 sGPR:$rd, sGPR:$rs1, sGPR:$rd),
626 def : CompressPat<(OR32 sGPR:$rd, sGPR:$rd, sGPR:$rs2),
628 def : CompressPat<(OR32 sGPR:$rd, sGPR:$rs1, sGPR:$rd),
630 def : CompressPat<(XOR32 sGPR:$rd, sGPR:$rd, sGPR:$rs2),
632 def : CompressPat<(XOR32 sGPR:$rd, sGPR:$rs1, sGPR:$rd),
637 def : CompressPat<(NOR32 sGPR:$rd, sGPR:$rd, sGPR:$rs2),
639 def : CompressPat<(LSL32 sGPR:$rd, sGPR:$rd, sGPR:$rs2),
641 def : CompressPat<(LSR32 sGPR:$rd, sGPR:$rd, sGPR:$rs2),
643 def : CompressPat<(ASR32 sGPR:$rd, sGPR:$rd, sGPR:$rs2),
[all …]
/llvm-project-15.0.7/llvm/lib/Target/RISCV/
H A DRISCVInstrInfoZb.td298 bits<5> rd;
318 bits<5> rd;
659 def : InstAlias<"zext.w $rd, $rs", (ADD_UW GPR:$rd, GPR:$rs, X0)>;
672 def : InstAlias<"rev.b $rd, $rs", (BREV8 GPR:$rd, GPR:$rs)>;
700 def : InstAlias<"rev16 $rd, $rs", (GREVI GPR:$rd, GPR:$rs, 0b10000)>;
702 def : InstAlias<"rev4 $rd, $rs", (GREVI GPR:$rd, GPR:$rs, 0b11100)>;
703 def : InstAlias<"rev2 $rd, $rs", (GREVI GPR:$rd, GPR:$rs, 0b11110)>;
704 def : InstAlias<"rev $rd, $rs", (GREVI GPR:$rd, GPR:$rs, 0b11111)>;
714 def : InstAlias<"orc16 $rd, $rs", (GORCI GPR:$rd, GPR:$rs, 0b10000)>;
715 def : InstAlias<"orc8 $rd, $rs", (GORCI GPR:$rd, GPR:$rs, 0b11000)>;
[all …]
H A DRISCVInstrInfoC.td275 bits<3> rd;
277 let Inst{9-7} = rd;
594 let rd = 0 in
700 def : InstAlias<"c.lw $rd, (${rs1})", (C_LW GPRC:$rd, GPRC:$rs1, 0)>;
702 def : InstAlias<"c.lwsp $rd, (${rs1})", (C_LWSP GPRC:$rd, SP:$rs1, 0)>;
707 def : InstAlias<"c.ld $rd, (${rs1})", (C_LD GPRC:$rd, GPRC:$rs1, 0)>;
709 def : InstAlias<"c.ldsp $rd, (${rs1})", (C_LDSP GPRC:$rd, SP:$rs1, 0)>;
714 def : InstAlias<"c.flw $rd, (${rs1})", (C_FLW FPR32C:$rd, GPRC:$rs1, 0)>;
716 def : InstAlias<"c.flwsp $rd, (${rs1})", (C_FLWSP FPR32C:$rd, SP:$rs1, 0)>;
721 def : InstAlias<"c.fld $rd, (${rs1})", (C_FLD FPR64C:$rd, GPRC:$rs1, 0)>;
[all …]
H A DRISCVInstrInfo.td519 let rd = 0;
581 let rd = 0;
672 let rd = 0;
678 let rd = 0;
684 let rd = 0;
690 let rd = 0;
697 let rd = 0;
707 let rd = 0;
755 let rd = 0;
761 let rd = 0;
[all …]
H A DRISCVInstrInfoF.td403 def : InstAlias<"flw $rd, (${rs1})", (FLW FPR32:$rd, GPR:$rs1, 0), 0>;
406 def : InstAlias<"fmv.s $rd, $rs", (FSGNJ_S FPR32:$rd, FPR32:$rs, FPR32:$rs)>;
407 def : InstAlias<"fabs.s $rd, $rs", (FSGNJX_S FPR32:$rd, FPR32:$rs, FPR32:$rs)>;
408 def : InstAlias<"fneg.s $rd, $rs", (FSGNJN_S FPR32:$rd, FPR32:$rs, FPR32:$rs)>;
420 def : InstAlias<"frcsr $rd", (CSRRS GPR:$rd, SysRegFCSR.Encoding, X0), 2>;
421 def : InstAlias<"fscsr $rd, $rs", (CSRRW GPR:$rd, SysRegFCSR.Encoding, GPR:$rs)>;
426 def : InstAlias<"frsr $rd", (CSRRS GPR:$rd, SysRegFCSR.Encoding, X0), 0>;
427 def : InstAlias<"fssr $rd, $rs", (CSRRW GPR:$rd, SysRegFCSR.Encoding, GPR:$rs), 0>;
430 def : InstAlias<"frrm $rd", (CSRRS GPR:$rd, SysRegFRM.Encoding, X0), 2>;
431 def : InstAlias<"fsrm $rd, $rs", (CSRRW GPR:$rd, SysRegFRM.Encoding, GPR:$rs)>;
[all …]
/llvm-project-15.0.7/llvm/test/MC/Sparc/
H A Dsparc-special-registers.s4 ! CHECK: rd %y, %i0 ! encoding: [0xb1,0x40,0x00,0x00]
5 rd %y, %i0
7 ! CHECK: rd %asr1, %i0 ! encoding: [0xb1,0x40,0x40,0x00]
8 rd %asr1, %i0
16 ! CHECK: rd %asr15, %g0 ! encoding: [0x81,0x43,0xc0,0x00]
17 rd %asr15, %g0
19 ! CHECK: rd %psr, %i0 ! encoding: [0xb1,0x48,0x00,0x00]
20 rd %psr, %i0
23 rd %wim, %i0
26 rd %tbr, %i0
[all …]
/llvm-project-15.0.7/llvm/lib/Target/MSP430/
H A DMSP430InstrInfo.td233 let rd = 0;
303 (outs GR16:$rd), (ins), "pop\t$rd", []> {
632 "rra.b\t$rd",
637 "rra\t$rd",
644 "rrc.b\t$rd",
649 "rrc\t$rd",
656 "sxt\t$rd",
793 (outs), (ins GR8:$rd, indreg:$rs), "cmp.b\t$rs, $rd", []>;
795 (outs), (ins GR16:$rd, indreg:$rs), "cmp\t$rs, $rd", []>;
798 (outs), (ins GR8:$rd, postreg:$rs), "cmp.b\t$rs, $rd", []>;
[all …]
/llvm-project-15.0.7/llvm/lib/Target/LoongArch/
H A DLoongArchInstrFormats.td51 bits<5> rd;
65 bits<5> rd;
81 bits<5> rd;
98 bits<5> rd;
114 bits<5> rd;
129 bits<5> rd;
144 bits<5> rd;
159 bits<5> rd;
174 bits<5> rd;
189 bits<5> rd;
[all …]
H A DLoongArchInstrInfo.td204 : Fmt3R<op, (outs GPR:$rd), (ins GPR:$rj, GPR:$rk), opstr, "$rd, $rj, $rk">;
206 : Fmt2R<op, (outs GPR:$rd), (ins GPR:$rj), opstr, "$rd, $rj">;
216 "$rd, $rj, $imm5">;
227 : Fmt1RI20<op, (outs GPR:$rd), (ins ImmOpnd:$imm20), opstr, "$rd, $imm20">;
233 : Fmt2R<op, (outs GPR:$rd, GPR:$rj), (ins), opstr, "$rd, $rj">;
255 : Fmt3R<op, (outs GPR:$rd), (ins GPR:$rj, GPR:$rk), opstr, "$rd, $rj, $rk">;
267 "$rd, $rj, $rk">;
278 : Fmt3R<op, (outs GPR:$rd), (ins GPR:$rk, GPR:$rj), opstr, "$rd, $rk, $rj">;
291 : Fmt2R<op, (outs GPR:$rd), (ins GPR:$rj), opstr, "$rd, $rj">;
294 : Fmt2R<op, (outs), (ins GPR:$rd, GPR:$rj), opstr, "$rd, $rj">;
[all …]
/llvm-project-15.0.7/llvm/lib/Target/AVR/
H A DAVRInstrInfo.td621 : $rd),
632 : $rd),
878 : $rd),
932 def : InstAlias<"tst\t$rd", (ANDRdRr GPR8 : $rd, GPR8 : $rd)>;
2102 def CLR : InstAlias<"clr\t$rd", (EORRdRr GPR8 : $rd, GPR8 : $rd)>;
2108 def LSL : InstAlias<"lsl\t$rd", (ADDRdRr GPR8 : $rd, GPR8 : $rd)>;
2110 def ROL : InstAlias<"rol\t$rd", (ADCRdRr GPR8 : $rd, GPR8 : $rd)>;
2116 def : InstAlias<"ser\t$rd", (LDIRdK LD8 : $rd, 0xff), 0>;
2390 def CopyR1 : Pseudo<(outs GPR8:$rd), (ins), "clrz\t$rd", [(set i8:$rd, 0)]>;
2523 def : Pat<(AVRtst i8 : $rd), (ANDRdRr GPR8 : $rd, GPR8 : $rd)>;
[all …]
/llvm-project-15.0.7/llvm/lib/Target/Mips/
H A DMipsMTInstrInfo.td53 dag OutOperandList = (outs GPR32Opnd:$rd);
55 string AsmString = "mftr\t$rd, $rt, $u, $sel, $h";
61 dag OutOperandList = (outs GPR32Opnd:$rd);
63 string AsmString = "mttr\t$rt, $rd, $u, $sel, $h";
69 dag OutOperandList = (outs GPR32Opnd:$rs, GPR32Opnd:$rd);
71 string AsmString = "fork\t$rd, $rs, $rt";
77 dag OutOperandList = (outs GPR32Opnd:$rd);
79 string AsmString = "yield\t$rd, $rs";
123 "mftgpr $rd, $rt">, ASE_MT;
190 def : MipsInstAlias<"mftc0 $rd, $rt", (MFTC0 GPR32Opnd:$rd, COP0Opnd:$rt, 0),
[all …]
/llvm-project-15.0.7/lldb/source/Plugins/Process/FreeBSDKernel/
H A DProcessFreeBSDKernel.cpp289 ssize_t rd = 0; in DoReadMemory() local
290 rd = fvc_read(m_fvc, addr, buf, size); in DoReadMemory()
291 if (rd < 0 || static_cast<size_t>(rd) != size) { in DoReadMemory()
293 return rd > 0 ? rd : 0; in DoReadMemory()
295 return rd; in DoReadMemory()
316 ssize_t rd = 0; in DoReadMemory() local
317 rd = kvm_read2(m_kvm, addr, buf, size); in DoReadMemory()
318 if (rd < 0 || static_cast<size_t>(rd) != size) { in DoReadMemory()
320 return rd > 0 ? rd : 0; in DoReadMemory()
322 return rd; in DoReadMemory()

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