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/llvm-project-15.0.7/llvm/lib/Target/XCore/
H A DXCoreInstrFormats.td37 let Inst{15-11} = opc;
67 let Inst{15-11} = opc;
100 let Inst{15-10} = opc;
110 let Inst{31-26} = opc;
121 let Inst{15-6} = opc;
129 let Inst{31-22} = opc;
139 let Inst{15-10} = opc;
156 let Inst{4} = opc{0};
183 let Inst{4} = opc{0};
209 let Inst{4} = opc{0};
[all …]
/llvm-project-15.0.7/llvm/test/TableGen/
H A DDefmInsideMultiClass.td7 class Instruction<bits<4> opc, string Name> {
8 bits<4> opcode = opc;
12 multiclass basic_r<bits<4> opc> {
13 def rr : Instruction<opc, "rr">;
14 def rm : Instruction<opc, "rm">;
17 multiclass basic_s<bits<4> opc> {
18 defm SS : basic_r<opc>;
19 defm SD : basic_r<opc>;
22 multiclass basic_p<bits<4> opc> {
23 defm PS : basic_r<opc>;
[all …]
H A DLetInsideMultiClasses.td9 class Instruction<bits<4> opc, string Name> {
10 bits<4> opcode = opc;
15 multiclass basic_r<bits<4> opc> {
17 def rr : Instruction<opc, "rr">;
18 def rm : Instruction<opc, "rm">;
22 def rx : Instruction<opc, "rx">;
25 multiclass basic_ss<bits<4> opc> {
27 defm SS : basic_r<opc>;
30 defm SD : basic_r<opc>;
H A DBitsInit.td6 bits<2> opc = { 0, 1 };
9 bits<2> a = { opc, opc2 }; // error!
10 bits<2> b = { opc{0}, opc2{0} };
11 bits<2> c = { opc{1}, opc2{1} };
16 // CHECK: bits<2> opc = { 0, 1 };
/llvm-project-15.0.7/llvm/lib/Target/VE/
H A DVEInstrVec.td132 def "" : RVM<opc, (outs RC:$vx), dag_in,
140 defm "" : VLDbm<opcStr, opc, RC, dag_in>;
237 def "" : RVM<opc, (outs RC:$vx), dag_in,
407 def "" : RR<opc, (outs RCM:$vx), dag_in,
425 defm "" : LVMom<opcStr, opc, RCM>;
445 def "" : RV<opc, (outs RC:$vx), dag_in,
489 def "" : RV<opc, (outs RC:$vx), dag_in,
530 def "" : RV<opc, (outs RC:$vx), dag_in,
693 def "" : RV<opc, (outs RC:$vx), dag_in,
774 defm "" : RVMKom<opcStr, opc, RC, RCM>;
[all …]
H A DVEInstrInfo.td533 multiclass RRbm<string opcStr, bits<8>opc,
565 multiclass RRNCbm<string opcStr, bits<8>opc,
589 multiclass RRm<string opcStr, bits<8>opc,
597 multiclass RRNCm<string opcStr, bits<8>opc,
605 multiclass RRFm<string opcStr, bits<8>opc,
614 multiclass RRIm<string opcStr, bits<8>opc,
701 multiclass RRSWPm<string opcStr, bits<8>opc,
722 def ir : RR<opc, (outs I64:$sx),
726 def rm : RR<opc, (outs I64:$sx),
730 def im : RR<opc, (outs I64:$sx),
[all …]
H A DVEInstrInfo.cpp247 unsigned opc[2]; in insertBranch() local
254 opc[0] = VE::BRCFWir; in insertBranch()
255 opc[1] = VE::BRCFWrr; in insertBranch()
257 opc[0] = VE::BRCFLir; in insertBranch()
258 opc[1] = VE::BRCFLrr; in insertBranch()
262 opc[0] = VE::BRCFSir; in insertBranch()
263 opc[1] = VE::BRCFSrr; in insertBranch()
265 opc[0] = VE::BRCFDir; in insertBranch()
266 opc[1] = VE::BRCFDrr; in insertBranch()
270 BuildMI(&MBB, DL, get(opc[0])) in insertBranch()
[all …]
/llvm-project-15.0.7/llvm/lib/Target/AArch64/
H A DSVEInstrFormats.td3076 def _S : sve2_int_mla_by_indexed_elem<0b10, { opc{3}, 0b0, opc{2-1}, ?, opc{0} },
3084 def _D : sve2_int_mla_by_indexed_elem<0b11, { opc{3}, 0b0, opc{2-1}, ?, opc{0} },
3396 def _S : sve2_int_mul_by_indexed_elem<0b10, { opc{2-1}, ?, opc{0} }, asm,
3404 def _D : sve2_int_mul_by_indexed_elem<0b11, { opc{2-1}, ?, opc{0} }, asm,
3522 def _S : sve2_int_un_pred_arit<0b10, opc{2}, opc{1-0}, asm, ZPR32>,
3533 def _B : sve2_int_un_pred_arit<0b00, opc{2}, opc{1-0}, asm, ZPR8>,
3535 def _H : sve2_int_un_pred_arit<0b01, opc{2}, opc{1-0}, asm, ZPR16>,
3537 def _S : sve2_int_un_pred_arit<0b10, opc{2}, opc{1-0}, asm, ZPR32>,
3539 def _D : sve2_int_un_pred_arit<0b11, opc{2}, opc{1-0}, asm, ZPR64>,
3929 def _S : sve2_int_absdiff_accum<{ opc{1}, 0b0 }, { 0b010, opc{0} }, asm,
[all …]
H A DAArch64InstrFormats.td1509 let Inst{7-5} = opc;
1707 // case opc of
1718 let Inst{24-21} = opc;
1772 let Inst{23-21} = opc;
2021 let Inst{12-10} = opc;
11242 bits<3> opc = 0b000;
11275 bits<3> opc;
11294 let Sz = 0b00, Acq = Acq, Rel = Rel, opc = opc in
11296 let Sz = 0b01, Acq = Acq, Rel = Rel, opc = opc in
11298 let Sz = 0b10, Acq = Acq, Rel = Rel, opc = opc in
[all …]
/llvm-project-15.0.7/llvm/lib/Target/ARM/
H A DARMInstrFormats.td619 opc, asm, "", pattern>;
623 opc, asm, "", pattern>;
641 opc, asm, "", pattern> {
660 opc, asm, "", pattern> {
675 opc, asm, "", pattern> {
747 opc, asm, "", pattern> {
853 opc, asm, "", pattern> {
911 opc, asm, "", pattern> {
946 opc, asm, "", pattern> {
963 opc, asm, "", pattern> {
[all …]
H A DARMInstrThumb2.td842 opc, "\t$Rd, $Rn, $Rm",
929 opc, ".w\t$Rd, $Rn, $imm",
1127 opc, ".w\t$Rn, $imm",
1139 opc, ".w\t$Rn, $Rm",
1195 opc, "\t$Rt, $addr",
1288 opc, "\t$Rt, $addr",
2485 : T2I_pam<op22_20, op7_4, opc,
2490 : T2I_pam<op22_20, op7_4, opc, [],
2888 opc, "\t$Rd, $imm",
2901 opc, ".w\t$Rd, $Rm",
[all …]
H A DARMInstrVFP.td524 def H : AHbInp<0b11100, opc, 0,
530 def S : ASbInp<0b11100, opc, 0,
536 def D : ADbInp<0b11100, opc, 0,
553 def H : AHbInp<0b11101, 0b00, opc,
559 def S : ASbInp<0b11101, 0b00, opc,
565 def D : ADbInp<0b11101, 0b00, opc,
1992 class BF16_VCVT<string opc, bits<2> op7_6>
2829 let Inst{20} = opc;
2835 let mayLoad = opc;
2836 let mayStore = !if(opc, 0b0, 0b1);
[all …]
H A DARMInstrInfo.td1734 opc, "\t$Rn, $imm",
1748 opc, "\t$Rn, $Rm",
1766 opc, "\t$Rn, $shift",
1783 opc, "\t$Rn, $shift",
3924 : AAI<op27_20, op11_4, opc,
3931 : AAI<op27_20, op11_4, opc,
4487 multiclass AI_smul<string opc> {
4526 multiclass AI_smla<string opc> {
4646 multiclass AI_smld<bit sub, string opc> {
5409 opc, asm, "", pattern> {
[all …]
/llvm-project-15.0.7/llvm/lib/Target/X86/
H A DX86InstrAVX512.td2178 def rr : AVX512BI<opc, MRMSrcReg,
2183 def rm : AVX512BI<opc, MRMSrcMem,
2188 def rrk : AVX512BI<opc, MRMSrcReg,
2194 def rmk : AVX512BI<opc, MRMSrcMem,
2206 def rmb : AVX512BI<opc, MRMSrcMem,
2211 def rmbk : AVX512BI<opc, MRMSrcMem,
2316 def rri : AVX512AIi8<opc, MRMSrcReg,
11686 def ri : AVX512<opc, MRMr,
11691 def mi : AVX512<opc, MRMm,
11724 def rr : AVX512BI<opc, MRMSrcReg,
[all …]
H A DX86InstrXOP.td96 def rr : IXOP<opc, MRMSrcReg4VOp3, (outs VR128:$dst),
102 def rm : IXOP<opc, MRMSrcMem, (outs VR128:$dst),
109 def mr : IXOP<opc, MRMSrcMem4VOp3, (outs VR128:$dst),
118 def rr_REV : IXOP<opc, MRMSrcReg, (outs VR128:$dst),
142 def ri : IXOPi8<opc, MRMSrcReg, (outs VR128:$dst),
148 def mi : IXOPi8<opc, MRMSrcMem, (outs VR128:$dst),
171 def rr : IXOPi8Reg<opc, MRMSrcReg, (outs VR128:$dst),
248 def ri : IXOPi8<opc, MRMSrcReg, (outs VR128:$dst),
256 def mi : IXOPi8<opc, MRMSrcMem, (outs VR128:$dst),
331 def rrr : IXOPi8Reg<opc, MRMSrcReg, (outs RC:$dst),
[all …]
H A DX86InstrFMA.td39 def r : FMA3<opc, MRMSrcReg, (outs RC:$dst),
47 def m : FMA3<opc, MRMSrcMem, (outs RC:$dst),
60 def r : FMA3<opc, MRMSrcReg, (outs RC:$dst),
67 def m : FMA3<opc, MRMSrcMem, (outs RC:$dst),
80 def r : FMA3<opc, MRMSrcReg, (outs RC:$dst),
181 def r : FMA3S<opc, MRMSrcReg, (outs RC:$dst),
189 def m : FMA3S<opc, MRMSrcMem, (outs RC:$dst),
202 def r : FMA3S<opc, MRMSrcReg, (outs RC:$dst),
209 def m : FMA3S<opc, MRMSrcMem, (outs RC:$dst),
222 def r : FMA3S<opc, MRMSrcReg, (outs RC:$dst),
[all …]
H A DX86Instr3DNow.td28 multiclass I3DNow_binop_rm_int<bits<8> opc, string Mn,
32 def rr : I3DNow_binop<opc, MRMSrcReg, (ins VR64:$src1, VR64:$src2), Mn,
36 def rm : I3DNow_binop<opc, MRMSrcMem, (ins VR64:$src1, i64mem:$src2), Mn,
43 multiclass I3DNow_conv_rm_int<bits<8> opc, string Mn,
45 def rr : I3DNow_conv<opc, MRMSrcReg, (ins VR64:$src), Mn,
49 def rm : I3DNow_conv<opc, MRMSrcMem, (ins i64mem:$src), Mn,
H A DX86InstrMMX.td37 def rr : MMXI<opc, MRMSrcReg, (outs VR64:$dst),
44 def rm : MMXI<opc, MRMSrcMem, (outs VR64:$dst),
55 def rr : MMXI<opc, MRMSrcReg, (outs VR64:$dst),
60 def rm : MMXI<opc, MRMSrcMem, (outs VR64:$dst),
74 multiclass SS3I_unop_rm_int_mm<bits<8> opc, string OpcodeStr,
89 multiclass SS3I_binop_rm_int_mm<bits<8> opc, string OpcodeStr,
93 def rr : MMXSS38I<opc, MRMSrcReg, (outs VR64:$dst),
98 def rm : MMXSS38I<opc, MRMSrcMem, (outs VR64:$dst),
134 multiclass sse12_cvt_pint_3addr<bits<8> opc, RegisterClass SrcRC,
137 def rr : MMXPI<opc, MRMSrcReg, (outs DstRC:$dst),
[all …]
H A DX86InstrSSE.td654 def PSrm : PI<opc, MRMSrcMem,
660 def PDrm : PI<opc, MRMSrcMem,
2102 def rr : PI<opc, MRMSrcReg,
2107 def rm : PI<opc, MRMSrcMem,
3765 def rr : PDI<opc, MRMSrcReg,
3774 def rm : PDI<opc, MRMSrcMem,
3790 def rr : SS48I<opc, MRMSrcReg,
3799 def rm : SS48I<opc, MRMSrcMem,
3866 def rr : PDI<opc, MRMSrcReg,
3873 def rm : PDI<opc, MRMSrcMem,
[all …]
/llvm-project-15.0.7/clang/lib/StaticAnalyzer/Checkers/
H A DMallocOverflowSecurityChecker.cpp83 BinaryOperatorKind opc = binop->getOpcode(); in CheckMallocArgument() local
85 if (mulop == nullptr && opc == BO_Mul) in CheckMallocArgument()
87 if (opc != BO_Mul && opc != BO_Add && opc != BO_Sub && opc != BO_Shl) in CheckMallocArgument()
95 if (EvaluatesToZero(maxVal, opc)) in CheckMallocArgument()
97 } else if ((opc == BO_Add || opc == BO_Mul) && in CheckMallocArgument()
100 if (EvaluatesToZero(maxVal, opc)) in CheckMallocArgument()
/llvm-project-15.0.7/lld/MachO/Arch/
H A DARM64.cpp222 uint8_t opc = (insn >> 22) & 3; in parseLdr() local
232 ldr.extendType = static_cast<ExtendType>(opc); in parseLdr()
238 if (opc == 1) in parseLdr()
240 else if (size == 0 && opc == 3) in parseLdr()
310 uint8_t size, opc; in writeImmediateLdr() local
313 opc = 3; in writeImmediateLdr()
315 opc = ldr.extendType; in writeImmediateLdr()
319 write32le(loc, opcode | (immBits << 10) | (opc << 22) | (size << 30)); in writeImmediateLdr()
/llvm-project-15.0.7/lld/ELF/Arch/
H A DPPC64.cpp447 uint32_t opc = encoding & 0xfc000000; in getPPCLegacyInsn() local
451 if ((opc == 0xe4000000 || opc == 0xe8000000 || opc == 0xf4000000 || in getPPCLegacyInsn()
452 opc == 0xf8000000) && in getPPCLegacyInsn()
454 opc = encoding & 0xfc000003; in getPPCLegacyInsn()
455 else if (opc == 0xf4000000) in getPPCLegacyInsn()
456 opc = encoding & 0xfc000007; in getPPCLegacyInsn()
457 else if (opc == 0x18000000) in getPPCLegacyInsn()
458 opc = encoding & 0xfc00000f; in getPPCLegacyInsn()
462 if (!checkPPCLegacyInsn(opc)) in getPPCLegacyInsn()
464 return static_cast<PPCLegacyInsn>(opc); in getPPCLegacyInsn()
/llvm-project-15.0.7/lldb/source/Plugins/Instruction/ARM64/
H A DEmulateInstructionARM64.cpp694 uint32_t opc = Bits32(opcode, 31, 30); in EmulateLDPSTP() local
717 if (opc == 3) in EmulateLDPSTP()
721 scale = 2 + UInt(opc); in EmulateLDPSTP()
723 scale = (opc & 2) ? 3 : 2; in EmulateLDPSTP()
724 is_signed = (opc & 1) != 0; in EmulateLDPSTP()
918 uint32_t opc = Bits32(opcode, 23, 22); in EmulateLDRSTRImm() local
946 if (Bit32(opc, 1) == 0) { in EmulateLDRSTRImm()
947 memop = Bit32(opc, 0) == 1 ? MemOp_LOAD : MemOp_STORE; in EmulateLDRSTRImm()
950 if (size == 2 && Bit32(opc, 0) == 1) in EmulateLDRSTRImm()
/llvm-project-15.0.7/llvm/lib/Target/PowerPC/
H A DPPCInstrAltivec.td270 !strconcat(opc, " $vD, $vA, $vB, $vC"), IIC_VecFP,
278 !strconcat(opc, " $vD, $vA, $vB, $vC"), IIC_VecFP,
286 !strconcat(opc, " $vD, $vA, $vB, $vC"), IIC_VecFP,
293 !strconcat(opc, " $vD, $vA, $vB"), IIC_VecFP,
301 !strconcat(opc, " $vD, $vA, $vB"), IIC_VecFP,
309 !strconcat(opc, " $vD, $vA, $vB"), IIC_VecFP,
313 class VX2_Int_SP<bits<11> xo, string opc, Intrinsic IntID>
315 !strconcat(opc, " $vD, $vB"), IIC_VecFP,
323 !strconcat(opc, " $vD, $vB"), IIC_VecFP,
328 !strconcat(opc, " $vD, $vA"), IIC_VecFP,
[all …]
/llvm-project-15.0.7/llvm/lib/Target/Hexagon/
H A DHexagonNewValueJump.cpp681 unsigned opc = getNewValueJumpOpcode(cmpInstr, cmpOp2, in runOnMachineFunction() local
685 opc = QII->getInvertedPredicatedOpcode(opc); in runOnMachineFunction()
688 NewMI = BuildMI(*MBB, jmpPos, dl, QII->get(opc)) in runOnMachineFunction()
694 NewMI = BuildMI(*MBB, jmpPos, dl, QII->get(opc)) in runOnMachineFunction()

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