| /llvm-project-15.0.7/llvm/lib/Target/Mips/ |
| H A D | MipsCCState.cpp | 162 if (Flags.isSRet()) { in PreAnalyzeFormalArgument()
189 if (Ins[i].Flags.isSRet()) { in PreAnalyzeFormalArgumentsForF128()
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| H A D | MipsCallLowering.cpp | 456 if (Arg.Flags[0].isSRet() && !Arg.Ty->isPointerTy()) in lowerCall()
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| H A D | MipsFastISel.cpp | 1513 if (Flag.isInReg() || Flag.isSRet() || Flag.isNest() || Flag.isByVal()) in fastLowerCall()
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| H A D | MipsISelLowering.cpp | 3760 if (Ins[InsIdx].Flags.isSRet()) { in LowerFormalArguments()
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| /llvm-project-15.0.7/flang/lib/Optimizer/CodeGen/ |
| H A D | Target.h | 39 bool isSRet() const { return sret; } in isSRet() function
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| H A D | TargetRewrite.cpp | 125 if (attr.isSRet()) { in rewriteCallComplexResultType()
351 if (std::get<fir::CodeGenSpecifics::Attributes>(tup).isSRet()) in lowerComplexSignatureRes()
746 if (attr.isSRet()) { in doComplexReturn()
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| /llvm-project-15.0.7/llvm/include/llvm/CodeGen/ |
| H A D | TargetCallingConv.h | 82 bool isSRet() const { return IsSRet; } in isSRet() function
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| /llvm-project-15.0.7/llvm/include/llvm/Target/ |
| H A D | TargetCallingConv.td | 92 class CCIfSRet<CCAction A> : CCIf<"ArgFlags.isSRet()", A> {}
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| /llvm-project-15.0.7/llvm/lib/Target/Sparc/ |
| H A D | SparcISelLowering.cpp | 45 assert (ArgFlags.isSRet()); in CC_Sparc_Assign_SRet()
449 if (Ins[InIdx].Flags.isSRet()) { in LowerFormalArguments_32()
778 if (!Outs.empty() && Caller.hasStructRetAttr() != Outs[0].Flags.isSRet()) in IsEligibleForTailCallOptimization()
897 if (Flags.isSRet()) { in LowerCall_32()
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| /llvm-project-15.0.7/llvm/lib/Target/M68k/ |
| H A D | M68kISelLowering.cpp | 189 if (!Flags.isSRet()) in callIsStructReturn()
203 if (!Flags.isSRet()) in argsAreStructReturn()
948 if (Ins[i].Flags.isSRet()) { in LowerFormalArguments()
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| /llvm-project-15.0.7/llvm/lib/CodeGen/GlobalISel/ |
| H A D | CallLowering.cpp | 126 if (OrigArg.Flags[0].isSRet() && isa<Instruction>(&Arg)) in lowerCall()
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| /llvm-project-15.0.7/llvm/lib/Target/MSP430/ |
| H A D | MSP430ISelLowering.cpp | 708 if (Ins[i].Flags.isSRet()) { in LowerCCCArguments()
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| /llvm-project-15.0.7/llvm/lib/Target/PowerPC/ |
| H A D | PPCFastISel.cpp | 1617 if (Flags.isInReg() || Flags.isSRet() || Flags.isNest() || Flags.isByVal()) in fastLowerCall()
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| /llvm-project-15.0.7/llvm/lib/Target/WebAssembly/ |
| H A D | WebAssemblyISelLowering.cpp | 1040 Outs[0].Flags.isSRet()) { in LowerCall()
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| /llvm-project-15.0.7/llvm/lib/Target/Hexagon/ |
| H A D | HexagonISelLowering.cpp | 416 bool IsStructRet = Outs.empty() ? false : Outs[0].Flags.isSRet(); in LowerCall()
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| /llvm-project-15.0.7/llvm/lib/Target/AArch64/ |
| H A D | AArch64FastISel.cpp | 3167 if (Flag.isInReg() || Flag.isSRet() || Flag.isNest() || Flag.isByVal() || in fastLowerCall()
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| /llvm-project-15.0.7/llvm/lib/Target/RISCV/ |
| H A D | RISCVISelLowering.cpp | 11115 auto IsCalleeStructRet = Outs.empty() ? false : Outs[0].Flags.isSRet(); in isEligibleForTailCallOptimization()
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| /llvm-project-15.0.7/llvm/lib/Target/AMDGPU/ |
| H A D | SIISelLowering.cpp | 2519 if (Arg.Flags.isSRet()) { in LowerFormalArguments()
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| /llvm-project-15.0.7/llvm/lib/Target/ARM/ |
| H A D | ARMISelLowering.cpp | 2338 bool isStructRet = (Outs.empty()) ? false : Outs[0].Flags.isSRet(); in LowerCall()
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| /llvm-project-15.0.7/llvm/lib/Target/X86/ |
| H A D | X86ISelLowering.cpp | 3561 if (!Flags.isSRet() || Flags.isInReg()) in hasCalleePopSRet()
4184 if (Ins[I].Flags.isSRet()) { in LowerFormalArguments()
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