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Searched refs:isSGPRClass (Results 1 – 14 of 14) sorted by relevance

/llvm-project-15.0.7/llvm/lib/Target/AMDGPU/
H A DSIRegisterInfo.h187 static bool isSGPRClass(const TargetRegisterClass *RC) { in isSGPRClass() function
193 return isSGPRClass(getRegClass(RCID)); in isSGPRClassID()
295 return !isSGPRClass(RC); in isDivergentRegClass()
H A DSIFixSGPRCopies.cpp172 return SrcRC != &AMDGPU::VReg_1RegClass && TRI.isSGPRClass(DstRC) && in isVGPRToSGPRCopy()
179 return DstRC != &AMDGPU::VReg_1RegClass && TRI.isSGPRClass(SrcRC) && in isSGPRToVGPRCopy()
231 if (!TRI->isSGPRClass(MRI.getRegClass(DstReg))) in foldVGPRCopyIntoRegSequence()
277 assert(TRI->isSGPRClass(SrcRC) && in foldVGPRCopyIntoRegSequence()
702 if (TRI->isSGPRClass(DstRC) && in runOnMachineFunction()
828 if (!TRI->isSGPRClass(OpRC) && OpRC != &AMDGPU::VS_32RegClass && in processPHINode()
856 if (TRI->isSGPRClass(RC)) in processPHINode()
H A DSIInstrInfo.cpp950 if (RI.isSGPRClass(RC)) { in copyPhysReg()
951 if (!RI.isSGPRClass(SrcRC)) { in copyPhysReg()
975 (SrcRC == RC || RI.isSGPRClass(SrcRC)))) { in copyPhysReg()
1099 if (RI.isSGPRClass(RegClass)) { in materializeImmediate()
1536 if (RI.isSGPRClass(RC)) { in storeRegToStackSlot()
1702 if (RI.isSGPRClass(RC)) { in loadRegFromStackSlot()
2757 return RI.isSGPRClass(RC); in canInsertSelect()
4861 else if (RI.isSGPRClass(RC)) in legalizeOpWithMove()
5762 if (VRC || !RI.isSGPRClass(getOpRegClass(MI, 0))) { in legalizeOperands()
7296 bool IsRequiredSGPR = RI.isSGPRClass(OpRC); in findUsedSGPR()
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H A DGCNPreRAOptimizations.cpp232 if ((RC->MC->getSizeInBits() != 64 || !TRI->isSGPRClass(RC)) && in runOnMachineFunction()
H A DGCNRegPressure.cpp77 return STI->isSGPRClass(RC) in getRegKind()
H A DAMDGPUTargetMachine.cpp80 return static_cast<const SIRegisterInfo &>(TRI).isSGPRClass(&RC); in onlyAllocateSGPRs()
85 return !static_cast<const SIRegisterInfo &>(TRI).isSGPRClass(&RC); in onlyAllocateVGPRs()
H A DGCNHazardRecognizer.cpp1194 if (MO.isDef() && TRI->isSGPRClass(TRI->getPhysRegClass(MO.getReg()))) { in fixSMEMtoVectorWriteHazards()
1275 if (MO.isDef() && TRI->isSGPRClass(TRI->getPhysRegClass(MO.getReg()))) in fixVcmpxExecWARHazard()
H A DAMDGPUTargetTransformInfo.cpp849 if (!RC || !TRI->isSGPRClass(RC)) in isInlineAsmSourceOfDivergence()
H A DSIRegisterInfo.cpp2240 bool IsSALU = isSGPRClass(TII->getOpRegClass(*MI, FIOperandNum)); in eliminateFrameIndex()
2678 return isSGPRClass(RC); in isSGPRReg()
H A DAMDGPUISelDAGToDAG.cpp1445 return RC && TRI.isSGPRClass(RC); in IsCopyFromSGPR()
2934 if (!RC || SIRI->isSGPRClass(RC)) in isVGPRImm()
H A DSIFoldOperands.cpp686 if (TRI->isSGPRClass(SrcRC) && TRI->hasVectorRegisters(DestRC)) { in foldOperand()
H A DSIISelLowering.cpp3802 if (TII->getRegisterInfo().isSGPRClass(IdxRC)) { in emitIndirectSrc()
3906 if (TII->getRegisterInfo().isSGPRClass(IdxRC)) { in emitIndirectDst()
12170 else if (SIRegisterInfo::isSGPRClass(RC)) in getRegForInlineAsmConstraint()
12842 if (!TRI->isSGPRClass(RC) && !isDivergent) in getRegClassFor()
12844 else if (TRI->isSGPRClass(RC) && isDivergent) in getRegClassFor()
12919 if (RC && SIRI->isSGPRClass(RC)) in requiresUniformRegister()
H A DAMDGPURegisterBankInfo.cpp282 if (TRI->isSGPRClass(&RC)) { in getRegBankFromRegClass()
H A DAMDGPUInstructionSelector.cpp161 TRI.isSGPRClass(SrcRC) ? AMDGPU::S_AND_B32 : AMDGPU::V_AND_B32_e32; in selectCOPY()