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Searched refs:isBeforeLegalizeOps (Results 1 – 13 of 13) sorted by relevance

/llvm-project-15.0.7/llvm/lib/Target/LoongArch/
H A DLoongArchISelLowering.cpp405 if (DCI.isBeforeLegalizeOps()) in performANDCombine()
468 if (DCI.isBeforeLegalizeOps()) in performSRLCombine()
519 if (DCI.isBeforeLegalizeOps()) in performORCombine()
/llvm-project-15.0.7/llvm/lib/CodeGen/SelectionDAG/
H A DTargetLowering.cpp601 !DCI.isBeforeLegalizeOps()); in SimplifyDemandedBits()
617 !DCI.isBeforeLegalizeOps()); in SimplifyDemandedBits()
3717 if (DCI.isBeforeLegalizeOps() || in foldSetCCWithAnd()
4156 (DCI.isBeforeLegalizeOps() || in SimplifySetCC()
4165 (DCI.isBeforeLegalizeOps() || in SimplifySetCC()
4398 if (DCI.isBeforeLegalizeOps() || in SimplifySetCC()
4451 if (DCI.isBeforeLegalizeOps() || in SimplifySetCC()
4580 if ((DCI.isBeforeLegalizeOps() || in SimplifySetCC()
4600 if ((DCI.isBeforeLegalizeOps() || in SimplifySetCC()
4843 if (DCI.isBeforeLegalizeOps() || in SimplifySetCC()
[all …]
/llvm-project-15.0.7/llvm/lib/Target/Mips/
H A DMipsISelLowering.cpp550 if (DCI.isBeforeLegalizeOps()) in performDivRemCombine()
659 if (DCI.isBeforeLegalizeOps()) in performSELECTCombine()
740 if (DCI.isBeforeLegalizeOps()) in performCMovFPCombine()
767 if (DCI.isBeforeLegalizeOps() || !Subtarget.hasExtractInsert()) in performANDCombine()
854 if (DCI.isBeforeLegalizeOps() || !Subtarget.hasExtractInsert()) in performORCombine()
1050 if (DCI.isBeforeLegalizeOps()) { in performSUBCombine()
1065 if (DCI.isBeforeLegalizeOps()) { in performADDCombine()
1100 if (DCI.isBeforeLegalizeOps() || !Subtarget.hasCnMips()) in performSHLCombine()
/llvm-project-15.0.7/llvm/lib/Target/XCore/
H A DXCoreISelLowering.cpp1605 !DCI.isBeforeLegalizeOps()); in PerformDAGCombine()
1621 !DCI.isBeforeLegalizeOps()); in PerformDAGCombine()
/llvm-project-15.0.7/llvm/lib/Target/AArch64/
H A DAArch64ISelLowering.cpp13973 if (DCI.isBeforeLegalizeOps()) in performXorCombine()
14233 if (DCI.isBeforeLegalizeOps()) in performMulCombine()
14577 if (ResTy == MVT::v4i64 && DCI.isBeforeLegalizeOps()) in performFDivCombine()
14865 if (DCI.isBeforeLegalizeOps()) in performSVEAndCombine()
15257 if (DCI.isBeforeLegalizeOps()) in performConcatVectorsCombine()
15347 if (DCI.isBeforeLegalizeOps()) in performExtractSubvectorCombine()
15414 if (DCI.isBeforeLegalizeOps()) in tryCombineFixedPointConvert()
15851 if (DCI.isBeforeLegalizeOps()) in performAddSubLongCombine()
16061 if (DCI.isBeforeLegalizeOps()) in tryCombineLongOpWithDup()
17426 if (DCI.isBeforeLegalizeOps()) in performPostLD1Combine()
[all …]
/llvm-project-15.0.7/llvm/lib/Target/X86/
H A DX86ISelLowering.cpp42422 if (!DCI.isBeforeLegalizeOps()) in combineCastedMaskArithmetic()
43398 if (DCI.isBeforeLegalizeOps()) in combineExtractWithShuffle()
44068 if (!DCI.isBeforeLegalizeOps()) in combineToExtendBoolVectorInReg()
47923 if (DCI.isBeforeLegalizeOps()) in combineAnd()
48437 if (DCI.isBeforeLegalizeOps()) in combineOr()
50919 if (DCI.isBeforeLegalizeOps()) in combineXor()
51694 if (!DCI.isBeforeLegalizeOps()) in combineSext()
51851 if (DCI.isBeforeLegalizeOps()) in combineZext()
52461 if (DCI.isBeforeLegalizeOps()) { in combineGatherScatter()
54186 if (DCI.isBeforeLegalizeOps()) in combineINSERT_SUBVECTOR()
[all …]
/llvm-project-15.0.7/llvm/lib/Target/AMDGPU/
H A DR600ISelLowering.cpp1850 if (DCI.isBeforeLegalizeOps() || in PerformDAGCombine()
H A DAMDGPUISelLowering.cpp4122 !DCI.isBeforeLegalizeOps()); in PerformDAGCombine()
H A DSIISelLowering.cpp9843 if (VT != MVT::i64 || DCI.isBeforeLegalizeOps()) in performOrCombine()
/llvm-project-15.0.7/llvm/include/llvm/CodeGen/
H A DTargetLowering.h3821 bool isBeforeLegalizeOps() const { return Level < AfterLegalizeVectorOps; } in isBeforeLegalizeOps() function
/llvm-project-15.0.7/llvm/lib/Target/Hexagon/
H A DHexagonISelLoweringHVX.cpp2589 if (DCI.isBeforeLegalizeOps()) in PerformHvxDAGCombine()
H A DHexagonISelLowering.cpp3300 if (DCI.isBeforeLegalizeOps()) in PerformDAGCombine()
/llvm-project-15.0.7/llvm/lib/Target/PowerPC/
H A DPPCISelLowering.cpp14561 if (DCI.isBeforeLegalizeOps()) in expandVSXLoadForLE()
14627 if (DCI.isBeforeLegalizeOps()) in expandVSXStoreForLE()
17353 bool LegalOps = !DCI.isBeforeLegalizeOps(); in combineFMALike()