AArch64ISelLowering.cpp - OpenGrok cross reference for /llvm-project-15.0.7/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp

Lines Matching refs:isBeforeLegalizeOps

13973   if (DCI.isBeforeLegalizeOps())  in performXorCombine()
14233   if (DCI.isBeforeLegalizeOps())  in performMulCombine()
14577   if (ResTy == MVT::v4i64 && DCI.isBeforeLegalizeOps())  in performFDivCombine()
14865   if (DCI.isBeforeLegalizeOps())  in performSVEAndCombine()
15257   if (DCI.isBeforeLegalizeOps())  in performConcatVectorsCombine()
15347   if (DCI.isBeforeLegalizeOps())  in performExtractSubvectorCombine()
15414   if (DCI.isBeforeLegalizeOps())  in tryCombineFixedPointConvert()
15851   if (DCI.isBeforeLegalizeOps())  in performAddSubLongCombine()
16061   if (DCI.isBeforeLegalizeOps())  in tryCombineLongOpWithDup()
16801   if (!DCI.isBeforeLegalizeOps() && N->getOpcode() == ISD::ZERO_EXTEND &&  in performExtendCombine()
17426   if (DCI.isBeforeLegalizeOps())  in performPostLD1Combine()
17536                                         !DCI.isBeforeLegalizeOps());  in performTBISimplification()
17580   if (DCI.isBeforeLegalizeOps() && Value.getOpcode() == ISD::FP_ROUND &&  in performSTORECombine()
19171   if (DCI.isBeforeLegalizeOps())  in performSignExtendInRegCombine()
19413   if (DCI.isBeforeLegalizeOps() && ISD::isNormalLoad(N0.getNode()) &&  in performFPExtendCombine()