Lines Matching refs:isBeforeLegalizeOps

601                         !DCI.isBeforeLegalizeOps());  in SimplifyDemandedBits()
617 !DCI.isBeforeLegalizeOps()); in SimplifyDemandedBits()
2726 !DCI.isBeforeLegalizeOps()); in SimplifyDemandedVectorElts()
3717 if (DCI.isBeforeLegalizeOps() || in foldSetCCWithAnd()
4156 (DCI.isBeforeLegalizeOps() || in SimplifySetCC()
4165 (DCI.isBeforeLegalizeOps() || in SimplifySetCC()
4398 if (DCI.isBeforeLegalizeOps() || in SimplifySetCC()
4451 if (DCI.isBeforeLegalizeOps() || in SimplifySetCC()
4580 if ((DCI.isBeforeLegalizeOps() || in SimplifySetCC()
4600 if ((DCI.isBeforeLegalizeOps() || in SimplifySetCC()
4616 if (!VT.isVector() || DCI.isBeforeLegalizeOps()) { in SimplifySetCC()
4634 if (!VT.isVector() || DCI.isBeforeLegalizeOps()) { in SimplifySetCC()
4719 if (!VT.isVector() || DCI.isBeforeLegalizeOps()) { in SimplifySetCC()
4843 if (DCI.isBeforeLegalizeOps() || in SimplifySetCC()
4889 (DCI.isBeforeLegalizeOps() || in SimplifySetCC()
6151 if (!DCI.isBeforeLegalizeOps() && !isOperationLegalOrCustom(ISD::MUL, VT)) in prepareUREMEqFold()
6288 if (!DCI.isBeforeLegalizeOps() && !isOperationLegalOrCustom(ISD::SUB, VT)) in prepareUREMEqFold()
6303 if (!DCI.isBeforeLegalizeOps() && !isOperationLegalOrCustom(ISD::ROTR, VT)) in prepareUREMEqFold()
6401 if (!DCI.isBeforeLegalizeOps() && !isOperationLegalOrCustom(ISD::MUL, VT)) in prepareSREMEqFold()
6556 if (!DCI.isBeforeLegalizeOps() && !isOperationLegalOrCustom(ISD::ADD, VT)) in prepareSREMEqFold()
6568 if (!DCI.isBeforeLegalizeOps() && !isOperationLegalOrCustom(ISD::ROTR, VT)) in prepareSREMEqFold()