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Searched refs:getRegClasses (Results 1 – 7 of 7) sorted by relevance

/llvm-project-15.0.7/llvm/utils/TableGen/
H A DRegisterBankEmitter.cpp181 for (const auto &PossibleSubclass : RegisterClassHierarchy.getRegClasses()) { in visitRegisterBankClasses()
198 BitVector BV(RegisterClassHierarchy.getRegClasses().size()); in visitRegisterBankClasses()
219 (RegisterClassHierarchy.getRegClasses().size() + 31) / 32); in emitBaseClassImplementation()
251 << RegisterClassHierarchy.getRegClasses().size() << ");\n"; in emitBaseClassImplementation()
302 for (const auto &Class : RegisterClassHierarchy.getRegClasses()) { in run()
H A DRegisterInfoEmitter.cpp135 const auto &RegisterClasses = Bank.getRegClasses(); in runEnums()
210 unsigned NumRCs = RegBank.getRegClasses().size(); in EmitRegUnitPressure()
217 for (const auto &RC : RegBank.getRegClasses()) { in EmitRegUnitPressure()
1039 const auto &RegisterClasses = RegBank.getRegClasses(); in runMCDesc()
1198 const auto &RegisterClasses = RegBank.getRegClasses(); in runTargetHeader()
1234 const auto &RegisterClasses = RegBank.getRegClasses(); in runTargetDesc()
1732 for (const CodeGenRegisterClass &RC : RegBank.getRegClasses()) { in debugDump()
1753 for (const CodeGenRegisterClass &SRC : RegBank.getRegClasses()) { in debugDump()
H A DCodeGenTarget.cpp302 auto &RegClasses = RegBank->getRegClasses(); in getRegNamespace()
367 auto &RegClasses = RegBank.getRegClasses(); in getSuperRegForSubReg()
425 for (const auto &RC : getRegBank().getRegClasses()) { in getRegisterVTs()
440 for (const auto &RC : getRegBank().getRegClasses()) in ReadLegalValueTypes()
H A DCodeGenRegisters.h739 std::list<CodeGenRegisterClass> &getRegClasses() { return RegClasses; } in getRegClasses() function
741 const std::list<CodeGenRegisterClass> &getRegClasses() const { in getRegClasses() function
H A DCodeGenRegisters.cpp974 auto &RegClasses = RegBank.getRegClasses(); in computeSubClasses()
1037 auto &RegClasses = RegBank.getRegClasses(); in getMatchingSubClassWithSubRegs()
1656 for (auto &RegClass : RegBank.getRegClasses()) { in computeUberSets()
1941 auto &RegClasses = getRegClasses(); in computeRegUnitSets()
2398 for (const auto &RC : getRegClasses()) { in getRegClassForRegister()
2439 for (const auto &RC : getRegClasses()) { in getMinimalPhysRegClass()
H A DDAGISelMatcherGen.cpp30 for (const auto &RC : T.getRegBank().getRegClasses()) { in getRegisterValueType()
H A DAsmMatcherEmitter.cpp1223 auto &RegClassList = Target.getRegBank().getRegClasses(); in buildRegisterClasses()