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Searched refs:getRegClassName (Results 1 – 25 of 29) sorted by relevance

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/llvm-project-15.0.7/llvm/lib/CodeGen/
H A DLiveStacks.cpp81 OS << " [" << TRI->getRegClassName(RC) << "]\n"; in print()
H A DRegisterBank.cpp108 OS << LS << TRI->getRegClassName(&RC); in print()
H A DRegAllocBase.cpp106 << TRI->getRegClassName(MRI->getRegClass(VirtReg->reg())) in allocatePhysRegs()
H A DRegisterClassInfo.cpp170 dbgs() << "AllocationOrder(" << TRI->getRegClassName(RC) << ") = ["; in compute()
H A DVirtRegMap.cpp152 << TRI->getRegClassName(MRI->getRegClass(Reg)) << "\n"; in print()
160 << "] " << TRI->getRegClassName(MRI->getRegClass(Reg)) << "\n"; in print()
H A DMachineVerifier.cpp2031 << TRI->getRegClassName(DRC) << " register.\n"; in visitMachineOperand()
2115 << TRI->getRegClassName( in visitMachineOperand()
2128 errs() << "Register class " << TRI->getRegClassName(RC) in visitMachineOperand()
2134 errs() << "Register class " << TRI->getRegClassName(RC) in visitMachineOperand()
2157 errs() << "Expected a " << TRI->getRegClassName(DRC) in visitMachineOperand()
2158 << " register, but got a " << TRI->getRegClassName(RC) in visitMachineOperand()
H A DExecutionDomainFix.cpp423 << TRI->getRegClassName(RC) << " **********\n"); in runOnMachineFunction()
H A DLiveRangeEdit.cpp493 << TRI->getRegClassName(MRI.getRegClass(LI.reg())) << '\n'; in calculateRegClassAndHint()
H A DTargetRegisterInfo.cpp179 OS << StringRef(TRI->getRegClassName(RegInfo.getRegClass(Reg))).lower(); in printRegClassOrBank()
H A DRegisterScavenging.cpp498 TRI->getRegClassName(&RC) + in spill()
H A DRegAllocPBQP.cpp894 const char *RegClassName = TRI->getRegClassName(MRI.getRegClass(VReg)); in PrintNodeInfo()
H A DAggressiveAntiDepBreaker.cpp532 LLVM_DEBUG(dbgs() << " " << TRI->getRegClassName(RC)); in GetRenameRegisters()
H A DRegAllocFast.cpp758 << " in class " << TRI->getRegClassName(&RC) in allocVirtReg()
H A DTargetInstrInfo.cpp1385 OS << ':' << TRI->getRegClassName(TRI->getRegClass(RCID)); in createMIROperandComment()
H A DInlineSpiller.cpp1209 << TRI.getRegClassName(MRI.getRegClass(edit.getReg())) in spill()
H A DRegisterCoalescer.cpp2014 << TRI->getRegClassName(CP.getNewRC()) << " with "; in joinCopy()
4172 << TRI->getRegClassName(MRI->getRegClass(Reg)) << '\n'); in runOnMachineFunction()
/llvm-project-15.0.7/llvm/include/llvm/CodeGen/
H A DTargetRegisterInfo.h756 const char *getRegClassName(const TargetRegisterClass *Class) const { in getRegClassName() function
757 return MCRegisterInfo::getRegClassName(Class->MC); in getRegClassName()
/llvm-project-15.0.7/llvm/lib/Target/AMDGPU/Disassembler/
H A DAMDGPUDisassembler.h108 const char* getRegClassName(unsigned RegClassID) const;
H A DAMDGPUDisassembler.cpp1042 const char* AMDGPUDisassembler::getRegClassName(unsigned RegClassID) const { in getRegClassName() function in AMDGPUDisassembler
1044 getRegClassName(&AMDGPUMCRegisterClasses[RegClassID]); in getRegClassName()
1067 return errOperand(Val, Twine(getRegClassName(RegClassID)) + in createRegOperand()
1105 *CommentStream << "Warning: " << getRegClassName(SRegClassID) in createSRegOperand()
/llvm-project-15.0.7/llvm/tools/llvm-exegesis/lib/
H A DMCInstrDescView.cpp273 << RegInfo.getRegClassName( in dump()
/llvm-project-15.0.7/llvm/lib/Target/Hexagon/
H A DHexagonRegisterInfo.cpp111 dbgs() << "Register class: " << getRegClassName(RC) << "\n"; in getCallerSavedRegs()
H A DHexagonBitTracker.cpp108 << TRI.getRegClassName(&RC) << '\n'; in mask()
/llvm-project-15.0.7/llvm/include/llvm/MC/
H A DMCRegisterInfo.h548 const char *getRegClassName(const MCRegisterClass *Class) const { in getRegClassName() function
/llvm-project-15.0.7/llvm/lib/CodeGen/MIRParser/
H A DMIParser.cpp280 std::make_pair(StringRef(TRI->getRegClassName(RC)).lower(), RC)); in initNames2RegClasses()
1503 Twine(TRI.getRegClassName(RegInfo.D.RC))); in parseRegisterClassOrBank()
/llvm-project-15.0.7/llvm/lib/Target/AArch64/
H A DAArch64LoadStoreOptimizer.cpp1501 << TRI->getRegClassName(RegClass) << "\n"); in tryToFindRegisterToRename()

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