1ef95969eSMatthias Braun //===-- LiveStacks.cpp - Live Stack Slot Analysis -------------------------===//
2ef95969eSMatthias Braun //
32946cd70SChandler Carruth // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
42946cd70SChandler Carruth // See https://llvm.org/LICENSE.txt for license information.
52946cd70SChandler Carruth // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6ef95969eSMatthias Braun //
7ef95969eSMatthias Braun //===----------------------------------------------------------------------===//
8ef95969eSMatthias Braun //
9ef95969eSMatthias Braun // This file implements the live stack slot analysis pass. It is analogous to
10ef95969eSMatthias Braun // live interval analysis except it's analyzing liveness of stack slots rather
11ef95969eSMatthias Braun // than registers.
12ef95969eSMatthias Braun //
13ef95969eSMatthias Braun //===----------------------------------------------------------------------===//
14ef95969eSMatthias Braun
15ef95969eSMatthias Braun #include "llvm/CodeGen/LiveStacks.h"
16ef95969eSMatthias Braun #include "llvm/CodeGen/TargetRegisterInfo.h"
17ef95969eSMatthias Braun #include "llvm/CodeGen/TargetSubtargetInfo.h"
18*989f1c72Sserge-sans-paille #include "llvm/InitializePasses.h"
19ef95969eSMatthias Braun using namespace llvm;
20ef95969eSMatthias Braun
21ef95969eSMatthias Braun #define DEBUG_TYPE "livestacks"
22ef95969eSMatthias Braun
23ef95969eSMatthias Braun char LiveStacks::ID = 0;
24ef95969eSMatthias Braun INITIALIZE_PASS_BEGIN(LiveStacks, DEBUG_TYPE,
25ef95969eSMatthias Braun "Live Stack Slot Analysis", false, false)
26ef95969eSMatthias Braun INITIALIZE_PASS_DEPENDENCY(SlotIndexes)
27ef95969eSMatthias Braun INITIALIZE_PASS_END(LiveStacks, DEBUG_TYPE,
28ef95969eSMatthias Braun "Live Stack Slot Analysis", false, false)
29ef95969eSMatthias Braun
30ef95969eSMatthias Braun char &llvm::LiveStacksID = LiveStacks::ID;
31ef95969eSMatthias Braun
getAnalysisUsage(AnalysisUsage & AU) const32ef95969eSMatthias Braun void LiveStacks::getAnalysisUsage(AnalysisUsage &AU) const {
33ef95969eSMatthias Braun AU.setPreservesAll();
34ef95969eSMatthias Braun AU.addPreserved<SlotIndexes>();
35ef95969eSMatthias Braun AU.addRequiredTransitive<SlotIndexes>();
36ef95969eSMatthias Braun MachineFunctionPass::getAnalysisUsage(AU);
37ef95969eSMatthias Braun }
38ef95969eSMatthias Braun
releaseMemory()39ef95969eSMatthias Braun void LiveStacks::releaseMemory() {
40ef95969eSMatthias Braun // Release VNInfo memory regions, VNInfo objects don't need to be dtor'd.
41ef95969eSMatthias Braun VNInfoAllocator.Reset();
42ef95969eSMatthias Braun S2IMap.clear();
43ef95969eSMatthias Braun S2RCMap.clear();
44ef95969eSMatthias Braun }
45ef95969eSMatthias Braun
runOnMachineFunction(MachineFunction & MF)46ef95969eSMatthias Braun bool LiveStacks::runOnMachineFunction(MachineFunction &MF) {
47ef95969eSMatthias Braun TRI = MF.getSubtarget().getRegisterInfo();
48ef95969eSMatthias Braun // FIXME: No analysis is being done right now. We are relying on the
49ef95969eSMatthias Braun // register allocators to provide the information.
50ef95969eSMatthias Braun return false;
51ef95969eSMatthias Braun }
52ef95969eSMatthias Braun
53ef95969eSMatthias Braun LiveInterval &
getOrCreateInterval(int Slot,const TargetRegisterClass * RC)54ef95969eSMatthias Braun LiveStacks::getOrCreateInterval(int Slot, const TargetRegisterClass *RC) {
55ef95969eSMatthias Braun assert(Slot >= 0 && "Spill slot indice must be >= 0");
56ef95969eSMatthias Braun SS2IntervalMap::iterator I = S2IMap.find(Slot);
57ef95969eSMatthias Braun if (I == S2IMap.end()) {
582bea69bfSDaniel Sanders I = S2IMap
592bea69bfSDaniel Sanders .emplace(
602bea69bfSDaniel Sanders std::piecewise_construct, std::forward_as_tuple(Slot),
612bea69bfSDaniel Sanders std::forward_as_tuple(Register::index2StackSlot(Slot), 0.0F))
62ef95969eSMatthias Braun .first;
63ef95969eSMatthias Braun S2RCMap.insert(std::make_pair(Slot, RC));
64ef95969eSMatthias Braun } else {
65ef95969eSMatthias Braun // Use the largest common subclass register class.
66ef95969eSMatthias Braun const TargetRegisterClass *OldRC = S2RCMap[Slot];
67ef95969eSMatthias Braun S2RCMap[Slot] = TRI->getCommonSubClass(OldRC, RC);
68ef95969eSMatthias Braun }
69ef95969eSMatthias Braun return I->second;
70ef95969eSMatthias Braun }
71ef95969eSMatthias Braun
72ef95969eSMatthias Braun /// print - Implement the dump method.
print(raw_ostream & OS,const Module *) const73ef95969eSMatthias Braun void LiveStacks::print(raw_ostream &OS, const Module*) const {
74ef95969eSMatthias Braun
75ef95969eSMatthias Braun OS << "********** INTERVALS **********\n";
76ef95969eSMatthias Braun for (const_iterator I = begin(), E = end(); I != E; ++I) {
77ef95969eSMatthias Braun I->second.print(OS);
78ef95969eSMatthias Braun int Slot = I->first;
79ef95969eSMatthias Braun const TargetRegisterClass *RC = getIntervalRegClass(Slot);
80ef95969eSMatthias Braun if (RC)
81ef95969eSMatthias Braun OS << " [" << TRI->getRegClassName(RC) << "]\n";
82ef95969eSMatthias Braun else
83ef95969eSMatthias Braun OS << " [Unknown]\n";
84ef95969eSMatthias Braun }
85ef95969eSMatthias Braun }
86