| /llvm-project-15.0.7/llvm/include/llvm/CodeGen/ |
| H A D | MachineInstr.h | 570 return getNumExplicitDefs() + MCID->getNumImplicitDefs();
604 unsigned getNumExplicitDefs() const;
655 operands_begin() + getNumExplicitDefs());
660 operands_begin() + getNumExplicitDefs());
665 return make_range(operands_begin() + getNumExplicitDefs(), operands_end());
669 return make_range(operands_begin() + getNumExplicitDefs(), operands_end());
672 return make_range(operands_begin() + getNumExplicitDefs(),
676 return make_range(operands_begin() + getNumExplicitDefs(),
1822 return getOperand(getNumExplicitDefs()).getIntrinsicID();
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| /llvm-project-15.0.7/llvm/lib/Target/AMDGPU/ |
| H A D | SIPostRABundler.cpp | 145 if (I->getNumExplicitDefs() != 0) in runOnMachineFunction()
157 if (I->getNumExplicitDefs() != 0) in runOnMachineFunction()
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| H A D | SIFixSGPRCopies.cpp | 1075 } else if (Inst->getNumExplicitDefs() != 0) { in lowerVGPR2SGPRCopies()
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| H A D | AMDGPULegalizerInfo.cpp | 3664 const unsigned FirstSrcOpIdx = MI.getNumExplicitDefs(); in legalizeUnsignedDIV_REM()
3690 const unsigned FirstSrcOpIdx = MI.getNumExplicitDefs(); in legalizeSignedDIV_REM()
4684 const bool HasReturn = MI.getNumExplicitDefs() != 0; in legalizeBufferAtomic()
4865 const unsigned NumDefs = MI.getNumExplicitDefs(); in legalizeImageIntrinsic()
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| H A D | AMDGPURegisterBankInfo.cpp | 312 for (unsigned I = 0, E = MI.getNumExplicitDefs(); I != E; ++I) { in addMappingFromTable()
1211 const int NumDefs = MI.getNumExplicitDefs(); in applyMappingImage()
3410 RsrcIdx += MI.getNumExplicitDefs() + 1; in getImageMapping()
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| H A D | SIFoldOperands.cpp | 1646 if (!ST->hasGFX90AInsts() || MI.getNumExplicitDefs() != 1) in tryFoldLoad()
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| H A D | AMDGPUInstructionSelector.cpp | 1560 const unsigned ArgOffset = MI.getNumExplicitDefs() + 1; in selectImageIntrinsic()
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| /llvm-project-15.0.7/llvm/lib/Target/WebAssembly/ |
| H A D | WebAssemblyMCInstLower.cpp | 172 unsigned NumVariadicDefs = MI->getNumExplicitDefs() - Desc.getNumDefs(); in lower()
270 OutMI.insert(OutMI.begin(), MCOperand::createImm(MI->getNumExplicitDefs())); in lower()
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| /llvm-project-15.0.7/llvm/lib/Target/SPIRV/ |
| H A D | SPIRVDuplicatesTracker.cpp | 84 if (MI.getNumExplicitDefs() > 0 && in buildDepsGraph()
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| H A D | SPIRVPreLegalizer.cpp | 104 unsigned NumOp = MI.getNumExplicitDefs() + AssignNameOperandShift; in foldConstantsIntoIntrinsics()
276 MI.getNumExplicitOperands() - MI.getNumExplicitDefs(); in generateAssignInstrs()
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| H A D | SPIRVInstructionSelector.cpp | 816 for (unsigned i = I.getNumExplicitDefs(); i < I.getNumExplicitOperands(); ++i) in selectConstVector()
1184 bool IsNull = I.getNumExplicitDefs() + 1 == I.getNumExplicitOperands(); in selectIntrinsic()
1192 for (unsigned i = I.getNumExplicitDefs() + 1; in selectIntrinsic()
1201 MIB.addUse(I.getOperand(I.getNumExplicitDefs() + 1).getReg()); in selectIntrinsic()
1202 for (unsigned i = I.getNumExplicitDefs() + 2; in selectIntrinsic()
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| /llvm-project-15.0.7/llvm/lib/Target/WebAssembly/Utils/ |
| H A D | WebAssemblyUtilities.cpp | 114 return MI.getOperand(MI.getNumExplicitDefs()); in getCalleeOp()
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| /llvm-project-15.0.7/llvm/lib/Target/RISCV/ |
| H A D | RISCVMCInstLower.cpp | 171 assert(MI->getNumExplicitDefs() == 1U + hasVLOutput); in lowerRISCVVMachineInstrToMCInst()
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| H A D | RISCVInsertVSETVLI.cpp | 387 if (RISCVII::hasSEWOp(TSFlags) && MI.getNumExplicitDefs() == 0) { in getDemanded()
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| H A D | RISCVInstrInfo.cpp | 2025 return MI.getNumExplicitDefs() == 2 && MI.modifiesRegister(RISCV::VL) && in isFaultFirstLoad()
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| /llvm-project-15.0.7/llvm/lib/Target/ARM/ |
| H A D | ARMFixCortexA57AES1742098Pass.cpp | 288 assert(MI.getNumExplicitOperands() == 3 && MI.getNumExplicitDefs() == 1 && in analyzeMF()
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| /llvm-project-15.0.7/llvm/lib/CodeGen/ |
| H A D | MachineCSE.cpp | 794 MI->getNumExplicitDefs() != 1) in isPRECandidate()
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| H A D | TwoAddressInstructionPass.cpp | 692 assert(mi->getNumExplicitDefs() == 1); in convertInstTo3Addr()
693 assert(NewMI->getNumExplicitDefs() == 1); in convertInstTo3Addr()
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| H A D | TargetInstrInfo.cpp | 1238 if (MI.getNumExplicitDefs() != 1) in describeLoadedValue()
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| H A D | MachineInstr.cpp | 698 unsigned MachineInstr::getNumExplicitDefs() const { in getNumExplicitDefs() function in MachineInstr
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| H A D | MachineVerifier.cpp | 1432 const MachineOperand &IntrIDOp = MI->getOperand(MI->getNumExplicitDefs()); in verifyPreISelGenericInstruction()
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| /llvm-project-15.0.7/llvm/lib/CodeGen/GlobalISel/ |
| H A D | GISelKnownBits.cpp | 57 assert(MI.getNumExplicitDefs() == 1 && in getKnownBits()
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| H A D | CombinerHelper.cpp | 2458 assert(MI.getNumExplicitDefs() == 1 && "Expected one explicit def?"); in replaceSingleDefInstWithOperand()
2469 assert(MI.getNumExplicitDefs() == 1 && "Expected one explicit def?"); in replaceSingleDefInstWithReg()
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| H A D | LegalizerHelper.cpp | 5073 unsigned NumDefs = MI.getNumExplicitDefs(); in narrowScalarAddSub()
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| /llvm-project-15.0.7/llvm/lib/Target/X86/ |
| H A D | X86InstrInfo.cpp | 8644 assert(Inst.getNumExplicitOperands() == 3 && Inst.getNumExplicitDefs() == 1 && in hasReassociableOperands()
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