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Searched refs:getKillRegState (Results 1 – 25 of 71) sorted by relevance

123

/llvm-project-15.0.7/llvm/lib/Target/AVR/
H A DAVRExpandPseudoInsts.cpp172 .addReg(DstLoReg, getKillRegState(DstIsKill)) in expandArith()
173 .addReg(SrcLoReg, getKillRegState(SrcIsKill)); in expandArith()
178 .addReg(DstHiReg, getKillRegState(DstIsKill)) in expandArith()
464 .addReg(DstLoReg, getKillRegState(DstIsKill)); in expand()
497 .addReg(DstLoReg, getKillRegState(DstIsKill)) in expand()
498 .addReg(SrcLoReg, getKillRegState(SrcIsKill)); in expand()
1325 .addReg(SrcLoReg, getKillRegState(SrcIsKill)) in expand()
1330 .addReg(SrcHiReg, getKillRegState(SrcIsKill)) in expand()
1435 .addReg(DstLoReg, getKillRegState(DstIsKill)) in expand()
1914 .addReg(DstLoReg, getKillRegState(DstIsKill)) in expandASRW7Rd()
[all …]
H A DAVRInstrInfo.cpp54 .addReg(SrcReg, getKillRegState(KillSrc)); in copyPhysReg()
63 .addReg(SrcHi, getKillRegState(KillSrc)); in copyPhysReg()
65 .addReg(SrcLo, getKillRegState(KillSrc)); in copyPhysReg()
68 .addReg(SrcLo, getKillRegState(KillSrc)); in copyPhysReg()
70 .addReg(SrcHi, getKillRegState(KillSrc)); in copyPhysReg()
85 .addReg(SrcReg, getKillRegState(KillSrc)); in copyPhysReg()
162 .addReg(SrcReg, getKillRegState(isKill)) in storeRegToStackSlot()
/llvm-project-15.0.7/llvm/lib/Target/Sparc/
H A DSparcInstrInfo.cpp323 .addReg(SrcReg, getKillRegState(KillSrc)); in copyPhysReg()
331 .addReg(SrcReg, getKillRegState(KillSrc)); in copyPhysReg()
335 .addReg(SrcReg, getKillRegState(KillSrc)); in copyPhysReg()
346 .addReg(SrcReg, getKillRegState(KillSrc)); in copyPhysReg()
363 .addReg(SrcReg, getKillRegState(KillSrc)); in copyPhysReg()
367 .addReg(SrcReg, getKillRegState(KillSrc)); in copyPhysReg()
411 .addReg(SrcReg, getKillRegState(isKill)).addMemOperand(MMO); in storeRegToStackSlot()
414 .addReg(SrcReg, getKillRegState(isKill)).addMemOperand(MMO); in storeRegToStackSlot()
417 .addReg(SrcReg, getKillRegState(isKill)).addMemOperand(MMO); in storeRegToStackSlot()
420 .addReg(SrcReg, getKillRegState(isKill)).addMemOperand(MMO); in storeRegToStackSlot()
[all …]
/llvm-project-15.0.7/llvm/lib/Target/VE/
H A DVERegisterInfo.cpp312 TmpReg, getKillRegState(true)); in processSTVM()
316 build(VE::SVMmr, TmpReg).addReg(SrcReg, getKillRegState(isKill)).addImm(3); in processSTVM()
359 build(VE::LVMir, DestReg).addImm(i).addReg(TmpReg, getKillRegState(true)); in processLDVM()
363 .addReg(TmpReg, getKillRegState(true)) in processLDVM()
368 .addReg(TmpReg, getKillRegState(true)) in processLDVM()
394 TmpReg, getKillRegState(true)); in processSTVM512()
405 TmpReg, getKillRegState(true)); in processSTVM512()
440 .addReg(TmpReg, getKillRegState(true)) in processLDVM512()
450 .addReg(TmpReg, getKillRegState(true)) in processLDVM512()
458 .addReg(TmpReg, getKillRegState(true)) in processLDVM512()
H A DVEInstrInfo.cpp366 .addReg(SrcReg, getKillRegState(KillSrc)) in copyPhysReg()
385 .addReg(SubTmp, getKillRegState(true)); in copyPhysReg()
390 .addReg(SrcReg, getKillRegState(KillSrc)); in copyPhysReg()
480 .addReg(SrcReg, getKillRegState(isKill)) in storeRegToStackSlot()
487 .addReg(SrcReg, getKillRegState(isKill)) in storeRegToStackSlot()
494 .addReg(SrcReg, getKillRegState(isKill)) in storeRegToStackSlot()
501 .addReg(SrcReg, getKillRegState(isKill)) in storeRegToStackSlot()
508 .addReg(SrcReg, getKillRegState(isKill)) in storeRegToStackSlot()
515 .addReg(SrcReg, getKillRegState(isKill)) in storeRegToStackSlot()
930 .addReg(Src, getKillRegState(KillSrc)); in expandPostRAPseudo()
[all …]
H A DVEISelLowering.cpp2033 .addReg(Tmp1, getKillRegState(true)) in prepareMBB()
2037 .addReg(Tmp2, getKillRegState(true)) in prepareMBB()
2049 .addReg(Tmp1, getKillRegState(true)) in prepareMBB()
2052 .addReg(Tmp2, getKillRegState(true)) in prepareMBB()
2137 .addReg(Tmp1, getKillRegState(true)) in prepareSymbol()
2140 .addReg(Tmp2, getKillRegState(true)) in prepareSymbol()
2355 .addReg(Tmp, getKillRegState(true)) in emitEHSjLjLongJmp()
2461 .addReg(Abort, getKillRegState(true)) in emitSjLjDispatchBlock()
2525 .addReg(Tmp1, getKillRegState(true)) in emitSjLjDispatchBlock()
2529 .addReg(Tmp2, getKillRegState(true)) in emitSjLjDispatchBlock()
[all …]
/llvm-project-15.0.7/llvm/lib/Target/ARM/
H A DThumb1InstrInfo.cpp53 .addReg(SrcReg, getKillRegState(KillSrc)) in copyPhysReg()
63 .addReg(SrcReg, getKillRegState(KillSrc)) in copyPhysReg()
71 .addReg(SrcReg, getKillRegState(KillSrc)); in copyPhysReg()
98 .addReg(SrcReg, getKillRegState(isKill)) in storeRegToStackSlot()
H A DMLxExpansionPass.cpp291 .addReg(Src1Reg, getKillRegState(Src1Kill)) in ExpandFPMLxInstruction()
292 .addReg(Src2Reg, getKillRegState(Src2Kill)); in ExpandFPMLxInstruction()
302 MIB.addReg(TmpReg, getKillRegState(true)) in ExpandFPMLxInstruction()
303 .addReg(AccReg, getKillRegState(AccKill)); in ExpandFPMLxInstruction()
305 MIB.addReg(AccReg).addReg(TmpReg, getKillRegState(true)); in ExpandFPMLxInstruction()
H A DARMLoadStoreOptimizer.cpp746 .addReg(Base, getKillRegState(KillOldBase)); in CreateLoadStoreMulti()
749 .addReg(Base, getKillRegState(KillOldBase)) in CreateLoadStoreMulti()
759 .addReg(Base, getKillRegState(KillOldBase)) in CreateLoadStoreMulti()
765 .addReg(Base, getKillRegState(KillOldBase)) in CreateLoadStoreMulti()
770 .addReg(Base, getKillRegState(KillOldBase)) in CreateLoadStoreMulti()
812 .addReg(Base, getKillRegState(BaseKill)); in CreateLoadStoreMulti()
821 MIB.addReg(Base, getKillRegState(BaseKill)); in CreateLoadStoreMulti()
851 MIB.addReg(Regs[0].first, getKillRegState(Regs[0].second)) in CreateLoadStoreDouble()
1351 .addReg(Base, getKillRegState(BaseKill)) in MergeBaseUpdateLSMultiple()
1811 .addReg(BaseReg, getKillRegState(BaseKill)) in FixInvalidRegPairOp()
[all …]
/llvm-project-15.0.7/llvm/lib/Target/LoongArch/
H A DLoongArchInstrInfo.cpp32 .addReg(SrcReg, getKillRegState(KillSrc)) in copyPhysReg()
49 .addReg(SrcReg, getKillRegState(KillSrc)); in copyPhysReg()
79 .addReg(SrcReg, getKillRegState(IsKill)) in storeRegToStackSlot()
/llvm-project-15.0.7/llvm/lib/Target/BPF/
H A DBPFInstrInfo.cpp37 .addReg(SrcReg, getKillRegState(KillSrc)); in copyPhysReg()
40 .addReg(SrcReg, getKillRegState(KillSrc)); in copyPhysReg()
135 .addReg(SrcReg, getKillRegState(IsKill)) in storeRegToStackSlot()
140 .addReg(SrcReg, getKillRegState(IsKill)) in storeRegToStackSlot()
/llvm-project-15.0.7/llvm/lib/Target/CSKY/
H A DCSKYInstrInfo.cpp428 .addReg(SrcReg, getKillRegState(IsKill)) in storeRegToStackSlot()
484 .addReg(SrcReg, getKillRegState(KillSrc)) in copyPhysReg()
489 .addReg(SrcReg, getKillRegState(KillSrc)) in copyPhysReg()
500 .addReg(SrcReg, getKillRegState(KillSrc)); in copyPhysReg()
508 .addReg(DestReg, getKillRegState(true)) in copyPhysReg()
509 .addReg(DestReg, getKillRegState(true)) in copyPhysReg()
510 .addReg(SrcReg, getKillRegState(true)); in copyPhysReg()
561 .addReg(SrcReg, getKillRegState(KillSrc)); in copyPhysReg()
H A DCSKYRegisterInfo.cpp210 .addReg(NewReg, getKillRegState(true)) in eliminateFrameIndex()
230 .addReg(NewReg, getKillRegState(true)) in eliminateFrameIndex()
231 .addReg(NewReg, getKillRegState(true)) in eliminateFrameIndex()
240 .addReg(NewReg, getKillRegState(true)) in eliminateFrameIndex()
/llvm-project-15.0.7/llvm/lib/Target/X86/
H A DX86InstrBuilder.h159 return addOffset(MIB.addReg(Reg, getKillRegState(isKill)), Offset); in addRegOffset()
167 return MIB.addReg(Reg1, getKillRegState(isKill1)).addImm(1) in addRegReg()
168 .addReg(Reg2, getKillRegState(isKill2)).addImm(0).addReg(0); in addRegReg()
/llvm-project-15.0.7/llvm/lib/Target/XCore/
H A DXCoreRegisterInfo.cpp77 .addReg(Reg, getKillRegState(MI.getOperand(0).isKill())) in InsertFPImmInst()
113 .addReg(Reg, getKillRegState(MI.getOperand(0).isKill())) in InsertFPConstInst()
147 .addReg(Reg, getKillRegState(MI.getOperand(0).isKill())) in InsertSPImmInst()
190 .addReg(Reg, getKillRegState(MI.getOperand(0).isKill())) in InsertSPConstInst()
H A DXCoreInstrInfo.cpp340 .addReg(SrcReg, getKillRegState(KillSrc)) in copyPhysReg()
352 .addReg(SrcReg, getKillRegState(KillSrc)); in copyPhysReg()
375 .addReg(SrcReg, getKillRegState(isKill)) in storeRegToStackSlot()
/llvm-project-15.0.7/llvm/lib/Target/MSP430/
H A DMSP430InstrInfo.cpp54 .addReg(SrcReg, getKillRegState(isKill)).addMemOperand(MMO); in storeRegToStackSlot()
58 .addReg(SrcReg, getKillRegState(isKill)).addMemOperand(MMO); in storeRegToStackSlot()
103 .addReg(SrcReg, getKillRegState(KillSrc)); in copyPhysReg()
/llvm-project-15.0.7/llvm/lib/Target/AArch64/
H A DAArch64AdvSIMDScalarPass.cpp278 .addReg(Src, getKillRegState(IsKill)); in insertCopy()
363 .addReg(Src0, getKillRegState(KillSrc0), SubReg0) in transformInstruction()
364 .addReg(Src1, getKillRegState(KillSrc1), SubReg1); in transformInstruction()
H A DAArch64SIMDInstrOpt.cpp434 unsigned Src0IsKill = getKillRegState(MI.getOperand(1).isKill()); in optimizeVectElement()
436 unsigned Src1IsKill = getKillRegState(MI.getOperand(2).isKill()); in optimizeVectElement()
442 unsigned Src2IsKill = getKillRegState(MI.getOperand(3).isKill()); in optimizeVectElement()
642 StRegKill[i] = getKillRegState(DefiningMI->getOperand(2*i+1).isKill()); in processSeqRegInst()
/llvm-project-15.0.7/llvm/lib/Target/PowerPC/
H A DPPCInstrInfo.cpp725 .addReg(VReg1, getKillRegState(true)) in generateLoadForNewConst()
927 .addReg(RegX, getKillRegState(KillX)) in reassociateFMA()
932 .addReg(RegY, getKillRegState(KillY)) in reassociateFMA()
944 .addReg(NewVRB, getKillRegState(true)) in reassociateFMA()
968 .addReg(RegX, getKillRegState(KillX)) in reassociateFMA()
1720 getKillRegState(KillSrc); in copyPhysReg()
1737 getKillRegState(KillSrc); in copyPhysReg()
1753 getKillRegState(KillSrc); in copyPhysReg()
1760 getKillRegState(KillSrc); in copyPhysReg()
1765 getKillRegState(KillSrc); in copyPhysReg()
[all …]
H A DPPCRegisterInfo.cpp736 .addReg(NegSizeReg, getKillRegState(KillNegSizeReg)); in lowerDynamicAlloc()
744 .addReg(NegSizeReg, getKillRegState(KillNegSizeReg)); in lowerDynamicAlloc()
824 .addReg(UnalNegSizeReg, getKillRegState(KillNegSizeReg)) in prepareDynamicAlloca()
841 .addReg(UnalNegSizeReg, getKillRegState(KillNegSizeReg)) in prepareDynamicAlloca()
941 .addReg(SrcReg, getKillRegState(MI.getOperand(0).isKill())); in lowerCRSpilling()
1217 .addReg(Reg, getKillRegState(IsKilled)), in spillRegPairs()
1221 .addReg(Reg + 1, getKillRegState(IsKilled)), in spillRegPairs()
1226 .addReg(Reg + 2, getKillRegState(IsKilled)), in spillRegPairs()
1291 .addReg(Reg, getKillRegState(IsKilled)), in lowerACCSpilling()
1355 .addReg(Reg, getKillRegState(IsKilled)), in lowerQuadwordSpilling()
[all …]
H A DPPCFrameLowering.cpp808 .addReg(TempReg, getKillRegState(true)) in emitPrologue()
842 .addReg(ScratchReg, getKillRegState(!HasROPProtect)) in emitPrologue()
860 .addReg(ScratchReg, getKillRegState(true)) in emitPrologue()
870 .addReg(TempReg, getKillRegState(true)) in emitPrologue()
967 .addReg(TOCReg, getKillRegState(true)) in emitPrologue()
1771 .addReg(TempReg, getKillRegState(i == e-1)); in emitEpilogue()
1847 .addReg(TempReg, getKillRegState(i == e-1)); in emitEpilogue()
2436 getKillRegState(true)), in spillCalleeSavedRegisters()
2452 .addReg(VSRContainingGPRs[Dst].first, getKillRegState(true)) in spillCalleeSavedRegisters()
2508 .addReg(MoveReg, getKillRegState(!CR4Spilled))); in restoreCRs()
[all …]
/llvm-project-15.0.7/llvm/lib/Target/Mips/
H A DMipsSEInstrInfo.cpp112 .addReg(SrcReg, RegState::Implicit | getKillRegState(KillSrc)); in copyPhysReg()
133 .addReg(SrcReg, getKillRegState(KillSrc)).addImm(1 << 4) in copyPhysReg()
139 .addReg(SrcReg, getKillRegState(KillSrc)); in copyPhysReg()
180 MIB.addReg(SrcReg, getKillRegState(KillSrc)); in copyPhysReg()
314 BuildMI(MBB, I, DL, get(Opc)).addReg(SrcReg, getKillRegState(isKill)) in storeRegToStack()
753 LoInst.addReg(SrcLo.getReg(), getKillRegState(SrcLo.isKill())); in expandPseudoMTLoHi()
754 HiInst.addReg(SrcHi.getReg(), getKillRegState(SrcHi.isKill())); in expandPseudoMTLoHi()
764 unsigned KillSrc = getKillRegState(Src.isKill()); in expandCvtFPInt()
/llvm-project-15.0.7/llvm/lib/Target/RISCV/
H A DRISCVRegisterInfo.cpp237 .addReg(FrameReg, getKillRegState(FrameRegIsKill)) in eliminateFrameIndex()
252 .addReg(FrameReg, getKillRegState(FrameRegIsKill)) in eliminateFrameIndex()
259 .addReg(FrameReg, getKillRegState(FrameRegIsKill)) in eliminateFrameIndex()
/llvm-project-15.0.7/llvm/lib/Target/M68k/
H A DM68kInstrBuilder.h51 return MIB.addImm(Offset).addReg(Reg, getKillRegState(IsKill)); in addRegIndirectWithDisp()

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