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Searched refs:getImplicitDefs (Results 1 – 20 of 20) sorted by relevance

/llvm-project-15.0.7/llvm/unittests/tools/llvm-exegesis/X86/
H A DSnippetGeneratorTest.cpp73 EXPECT_THAT(InstrInfo.get(Opcode).getImplicitDefs()[0], X86::AX); in TEST_F()
74 EXPECT_THAT(InstrInfo.get(Opcode).getImplicitDefs()[1], X86::EFLAGS); in TEST_F()
99 EXPECT_THAT(InstrInfo.get(Opcode).getImplicitDefs()[0], X86::EFLAGS); in TEST_F()
/llvm-project-15.0.7/bolt/lib/Core/
H A DMCPlusBuilder.cpp335 const MCPhysReg *ImplicitDefs = InstInfo.getImplicitDefs(); in getClobberedRegs()
352 const MCPhysReg *ImplicitDefs = InstInfo.getImplicitDefs(); in getTouchedRegs()
372 const MCPhysReg *ImplicitDefs = InstInfo.getImplicitDefs(); in getWrittenRegs()
/llvm-project-15.0.7/llvm/include/llvm/MC/
H A DMCInstrDesc.h587 const MCPhysReg *getImplicitDefs() const { return ImplicitDefs; } in getImplicitDefs() function
/llvm-project-15.0.7/llvm/lib/CodeGen/SelectionDAG/
H A DScheduleDAGFast.cpp431 for (const MCPhysReg *ImpDef = MCID.getImplicitDefs(); *ImpDef; ++ImpDef) { in getPhysicalRegisterVT()
531 for (const MCPhysReg *Reg = MCID.getImplicitDefs(); *Reg; ++Reg) { in DelayForLiveRegsBottomUp()
H A DInstrEmitter.cpp988 II.getImplicitDefs() != nullptr && !HasVRegVariadicDefs; in EmitMachineNode()
1091 Register Reg = II.getImplicitDefs()[i - NumDefs]; in EmitMachineNode()
1126 if (!UsedRegs.empty() || II.getImplicitDefs() || II.hasOptionalDef()) in EmitMachineNode()
H A DScheduleDAGRRList.cpp1286 for (const MCPhysReg *ImpDef = MCID.getImplicitDefs(); *ImpDef; ++ImpDef) { in getPhysicalRegisterVT()
1440 for (const MCPhysReg *Reg = MCID.getImplicitDefs(); *Reg; ++Reg) in DelayForLiveRegsBottomUp()
2858 = TII->get(SU->getNode()->getMachineOpcode()).getImplicitDefs(); in canClobberReachingPhysRegUse()
2894 const MCPhysReg *ImpDefs = TII->get(N->getMachineOpcode()).getImplicitDefs(); in canClobberPhysRegDefs()
2901 TII->get(SUNode->getMachineOpcode()).getImplicitDefs(); in canClobberPhysRegDefs()
H A DScheduleDAGSDNodes.cpp463 TII->get(N->getMachineOpcode()).getImplicitDefs()) { in AddSchedEdges()
/llvm-project-15.0.7/llvm/tools/llvm-exegesis/lib/
H A DMCInstrDescView.cpp131 for (const MCPhysReg *MCPhysReg = Description->getImplicitDefs(); in create()
/llvm-project-15.0.7/bolt/lib/Passes/
H A DRegReAssign.cpp159 const MCPhysReg *ImplicitDefs = Desc.getImplicitDefs(); in rankRegisters()
/llvm-project-15.0.7/llvm/lib/Target/Hexagon/MCTargetDesc/
H A DHexagonMCChecker.cpp109 if (const MCPhysReg *ImpDef = MCID.getImplicitDefs()) in init()
/llvm-project-15.0.7/llvm/lib/MCA/
H A DInstrBuilder.cpp397 Write.RegisterID = MCDesc.getImplicitDefs()[CurrentDef]; in populateWrites()
/llvm-project-15.0.7/llvm/lib/CodeGen/
H A DRDFGraph.cpp626 if (!D.getImplicitDefs() && !D.getImplicitUses()) in isFixedReg()
635 const MCPhysReg *ImpR = Op.isDef() ? D.getImplicitDefs() in isFixedReg()
H A DMachineInstr.cpp89 for (const MCPhysReg *ImpDefs = MCID->getImplicitDefs(); *ImpDefs; in addImplicitDefUseOperands()
/llvm-project-15.0.7/llvm/lib/Target/ARM/
H A DThumb2SizeReduction.cpp256 for (const MCPhysReg *Regs = MCID.getImplicitDefs(); *Regs; ++Regs) in HasImplicitCPSRDef()
/llvm-project-15.0.7/llvm/lib/Target/X86/MCTargetDesc/
H A DX86MCTargetDesc.cpp564 const MCPhysReg Reg = Desc.getImplicitDefs()[I]; in clearsSuperRegisters()
/llvm-project-15.0.7/llvm/lib/CodeGen/MIRParser/
H A DMIParser.cpp1363 for (const MCPhysReg *ImpDefs = MCID.getImplicitDefs(); *ImpDefs; ++ImpDefs) in verifyImplicitOperands()
/llvm-project-15.0.7/llvm/lib/MC/MCParser/
H A DAsmParser.cpp6056 ArrayRef<MCPhysReg> ImpDefs(Desc.getImplicitDefs(), in parseMSInlineAsm()
H A DMasmParser.cpp7450 ArrayRef<MCPhysReg> ImpDefs(Desc.getImplicitDefs(), in parseMSInlineAsm()
/llvm-project-15.0.7/llvm/lib/Target/PowerPC/
H A DPPCInstrInfo.cpp2737 for (const MCPhysReg *ImpDefs = NewDesc.getImplicitDefs(); in optimizeCompareInstr()
/llvm-project-15.0.7/llvm/lib/Target/AMDGPU/
H A DSIInstrInfo.cpp3509 if (const MCPhysReg *ImpDef = MI.getDesc().getImplicitDefs()) { in modifiesModeRegister()