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Searched refs:getFeatureBits (Results 1 – 25 of 106) sorted by relevance

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/llvm-project-15.0.7/llvm/test/TableGen/
H A DAsmPredicateCombiningRISCV.td62 // COMPRESS: if (STI.getFeatureBits()[arch::AsmCond1] &&
68 // COMPRESS: if (STI.getFeatureBits()[arch::AsmCond2a] &&
69 // COMPRESS-NEXT: STI.getFeatureBits()[arch::AsmCond2b] &&
75 // COMPRESS: if ((STI.getFeatureBits()[arch::AsmCond3a] || STI.getFeatureBits()[arch::AsmCond3…
81 // COMPRESS: if (STI.getFeatureBits()[arch::AsmCond1] &&
82 // COMPRESS-NEXT: STI.getFeatureBits()[arch::AsmCond2a] &&
83 // COMPRESS-NEXT: STI.getFeatureBits()[arch::AsmCond2b] &&
89 // COMPRESS: if (STI.getFeatureBits()[arch::AsmCond1] &&
90 // COMPRESS-NEXT: (STI.getFeatureBits()[arch::AsmCond3a] || STI.getFeatureBits()[arch::AsmCond3b]) …
/llvm-project-15.0.7/llvm/lib/Target/AMDGPU/Utils/
H A DAMDGPUBaseInfo.cpp745 if (STI->getFeatureBits().test(FeatureSGPRInitBug)) in getAddressableNumSGPRs()
767 if (STI->getFeatureBits().test(FeatureTrapHandler)) in getMinNumSGPRs()
784 if (STI->getFeatureBits().test(FeatureTrapHandler)) in getMaxNumSGPRs()
829 if (STI->getFeatureBits().test(FeatureGFX90AInsts)) in getVGPRAllocGranule()
844 if (STI->getFeatureBits().test(FeatureGFX90AInsts)) in getVGPREncodingGranule()
855 if (STI->getFeatureBits().test(FeatureGFX90AInsts)) in getTotalNumVGPRs()
872 if (STI->getFeatureBits().test(FeatureGFX90AInsts)) in getAddressableNumVGPRs()
1726 …return STI.getFeatureBits()[AMDGPU::FeatureMIMG_R128] && !STI.getFeatureBits()[AMDGPU::FeatureR128… in hasMIMG_R128()
1734 return STI.getFeatureBits()[AMDGPU::FeatureG16]; in hasG16()
1755 return STI.getFeatureBits()[AMDGPU::FeatureGFX9]; in isGFX9()
[all …]
/llvm-project-15.0.7/llvm/lib/Target/AMDGPU/MCTargetDesc/
H A DAMDGPUMCAsmInfo.cpp61 if (STI->getFeatureBits()[AMDGPU::FeatureNSAEncoding]) in getMaxInstLength()
65 if (STI->getFeatureBits()[AMDGPU::FeatureVOP3Literal]) in getMaxInstLength()
H A DSIMCCodeEmitter.cpp142 STI.getFeatureBits()[AMDGPU::FeatureInv2PiInlineImm]) in getLit16Encoding()
178 STI.getFeatureBits()[AMDGPU::FeatureInv2PiInlineImm]) in getLit32Encoding()
214 STI.getFeatureBits()[AMDGPU::FeatureInv2PiInlineImm]) in getLit64Encoding()
274 if (!isUInt<16>(Imm) && STI.getFeatureBits()[AMDGPU::FeatureVOP3Literal]) in getLitEncoding()
368 if ((bytes > 8 && STI.getFeatureBits()[AMDGPU::FeatureVOP3Literal]) || in encodeInstruction()
369 (bytes > 4 && !STI.getFeatureBits()[AMDGPU::FeatureVOP3Literal])) in encodeInstruction()
H A DR600MCCodeEmitter.cpp100 if (!(STI.getFeatureBits()[R600::FeatureCaymanISA])) { in encodeInstruction()
133 if ((STI.getFeatureBits()[R600::FeatureR600ALUInst]) && in encodeInstruction()
/llvm-project-15.0.7/llvm/lib/MC/
H A DMCInstPrinter.cpp70 return STI->getFeatureBits().test(C.Value); in matchAliasCondition()
72 return !STI->getFeatureBits().test(C.Value); in matchAliasCondition()
77 OrPredicateResult |= STI->getFeatureBits().test(C.Value); in matchAliasCondition()
81 OrPredicateResult |= !(STI->getFeatureBits().test(C.Value)); in matchAliasCondition()
H A DMCInstrInfo.cpp21 STI.getFeatureBits()[DeprecatedFeatures[Opcode]]) { in getDeprecatedInfo()
/llvm-project-15.0.7/llvm/lib/Target/AMDGPU/Disassembler/
H A DAMDGPUDisassembler.cpp543 if (STI.getFeatureBits()[AMDGPU::FeatureGFX90AInsts]) { in getInstruction()
563 if (STI.getFeatureBits()[AMDGPU::FeatureGFX90AInsts]) { in getInstruction()
711 if (STI.getFeatureBits()[AMDGPU::FeatureGFX11]) { in convertEXPInst()
733 if (STI.getFeatureBits()[AMDGPU::FeatureGFX9] || in convertSDWAInst()
734 STI.getFeatureBits()[AMDGPU::FeatureGFX10]) { in convertSDWAInst()
1650 if (STI.getFeatureBits()[AMDGPU::FeatureGFX9] || in decodeSDWASrc()
1651 STI.getFeatureBits()[AMDGPU::FeatureGFX10]) { in decodeSDWASrc()
1697 assert((STI.getFeatureBits()[AMDGPU::FeatureGFX9] || in decodeSDWAVopcDst()
1698 STI.getFeatureBits()[AMDGPU::FeatureGFX10]) && in decodeSDWAVopcDst()
1733 return STI.getFeatureBits()[AMDGPU::FeatureGFX90AInsts]; in isGFX90A()
[all …]
/llvm-project-15.0.7/llvm/lib/Target/WebAssembly/
H A DWebAssemblyTargetTransformInfo.cpp109 TM.getSubtargetImpl(*Caller)->getFeatureBits(); in areInlineCompatible()
111 TM.getSubtargetImpl(*Callee)->getFeatureBits(); in areInlineCompatible()
/llvm-project-15.0.7/llvm/lib/Target/Hexagon/MCTargetDesc/
H A DHexagonMCTargetDesc.cpp350 if (STI->getFeatureBits()[F]) in clearFeature()
355 return STI->getFeatureBits()[F]; in checkFeature()
526 llvm::FeatureBitset Features = X->getFeatureBits(); in createHexagonMCSubtargetInfo()
531 llvm::FeatureBitset Features = X->getFeatureBits(); in createHexagonMCSubtargetInfo()
535 X->setFeatureBits(completeHVXFeatures(X->getFeatureBits())); in createHexagonMCSubtargetInfo()
543 llvm::FeatureBitset Features = X->getFeatureBits(); in createHexagonMCSubtargetInfo()
/llvm-project-15.0.7/llvm/lib/Target/ARM/MCTargetDesc/
H A DARMAsmBackend.cpp210 bool HasThumb2 = STI.getFeatureBits()[ARM::FeatureThumb2]; in getRelaxedOpcode()
211 bool HasV8MBaselineOps = STI.getFeatureBits()[ARM::HasV8MBaselineOps]; in getRelaxedOpcode()
606 (!STI->getFeatureBits()[ARM::FeatureThumb2] && in adjustFixupValue()
607 !STI->getFeatureBits()[ARM::HasV8MBaselineOps] && in adjustFixupValue()
608 !STI->getFeatureBits()[ARM::HasV6MOps] && in adjustFixupValue()
681 if (!STI->getFeatureBits()[ARM::FeatureThumb2] && IsResolved) { in adjustFixupValue()
706 if (!STI->getFeatureBits()[ARM::FeatureThumb2] && in adjustFixupValue()
707 !STI->getFeatureBits()[ARM::HasV8MBaselineOps]) { in adjustFixupValue()
718 if (!STI->getFeatureBits()[ARM::FeatureThumb2]) { in adjustFixupValue()
H A DARMMCTargetDesc.cpp41 if (STI.getFeatureBits()[llvm::ARM::HasV7Ops] && in getMCRDeprecationInfo()
68 if (STI.getFeatureBits()[llvm::ARM::HasV7Ops] && in getMCRDeprecationInfo()
80 if (STI.getFeatureBits()[llvm::ARM::HasV7Ops] && in getMRCDeprecationInfo()
92 assert(!STI.getFeatureBits()[llvm::ARM::ModeThumb] && in getARMStoreDeprecationInfo()
108 assert(!STI.getFeatureBits()[llvm::ARM::ModeThumb] && in getARMLoadDeprecationInfo()
604 Addr += STI->getFeatureBits()[ARM::ModeThumb] ? 4 : 8; in evaluateMemoryOperandAddress()
639 return STI.getFeatureBits()[ARM::FeatureCoprocCDE0 + Coproc]; in isCDECoproc()
H A DARMAsmBackend.h31 return STI->getFeatureBits()[ARM::HasV6T2Ops]; in hasNOP()
/llvm-project-15.0.7/llvm/lib/Target/RISCV/Disassembler/
H A DRISCVDisassembler.cpp65 Decoder->getSubtargetInfo().getFeatureBits(); in DecodeGPRRegisterClass()
447 if (STI.getFeatureBits()[RISCV::FeatureStdExtZdinx] && in getInstruction()
448 !STI.getFeatureBits()[RISCV::Feature64Bit]) { in getInstruction()
459 if (STI.getFeatureBits()[RISCV::FeatureStdExtZfinx]) { in getInstruction()
478 if (!STI.getFeatureBits()[RISCV::Feature64Bit]) { in getInstruction()
/llvm-project-15.0.7/llvm/lib/Target/RISCV/
H A DRISCVSubtarget.cpp85 TargetABI = RISCVABI::computeTargetABI(TT, getFeatureBits(), ABIName); in initializeSubtargetDependencies()
86 RISCVFeatures::validate(TT, getFeatureBits()); in initializeSubtargetDependencies()
H A DRISCVAsmPrinter.cpp95 getSubtargetInfo().getFeatureBits()); in emitInstruction()
178 NewSTI.setFeatureBits(MF.getSubtarget().getFeatureBits()); in runOnMachineFunction()
/llvm-project-15.0.7/llvm/lib/Target/RISCV/MCTargetDesc/
H A DRISCVAsmBackend.cpp137 return STI.getFeatureBits()[RISCV::FeatureRelax] || ForceRelocs; in shouldForceRelocation()
357 bool HasStdExtC = STI->getFeatureBits()[RISCV::FeatureStdExtC]; in writeNopData()
587 if (!STI->getFeatureBits()[RISCV::FeatureRelax]) in shouldInsertExtraNopBytesForCodeAlign()
590 bool HasStdExtC = STI->getFeatureBits()[RISCV::FeatureStdExtC]; in shouldInsertExtraNopBytesForCodeAlign()
611 if (!STI->getFeatureBits()[RISCV::FeatureRelax]) in shouldInsertFixupForCodeAlign()
H A DRISCVELFStreamer.cpp36 const FeatureBitset &Features = STI.getFeatureBits(); in RISCVTargetELFStreamer()
153 const FeatureBitset &Features = STI.getFeatureBits(); in finish()
/llvm-project-15.0.7/llvm/lib/Target/LoongArch/
H A DLoongArchAsmPrinter.cpp31 MI->getOpcode(), getSubtargetInfo().getFeatureBits()); in emitInstruction()
/llvm-project-15.0.7/llvm/lib/Target/ARC/
H A DARCAsmPrinter.cpp53 getSubtargetInfo().getFeatureBits()); in emitInstruction()
/llvm-project-15.0.7/llvm/tools/llvm-exegesis/lib/X86/
H A DTarget.cpp871 if (STI.getFeatureBits()[X86::FeatureAVX512]) in setRegTo()
873 if (STI.getFeatureBits()[X86::FeatureAVX]) in setRegTo()
878 if (STI.getFeatureBits()[X86::FeatureAVX512]) in setRegTo()
880 if (STI.getFeatureBits()[X86::FeatureAVX]) in setRegTo()
884 if (STI.getFeatureBits()[X86::FeatureAVX512]) in setRegTo()
897 STI.getFeatureBits()[X86::FeatureAVX] ? X86::VLDMXCSR : X86::LDMXCSR, in setRegTo()
/llvm-project-15.0.7/llvm/lib/Target/Mips/AsmParser/
H A DMipsAsmParser.cpp475 FeatureBitset FeatureBits = STI.getFeatureBits(); in selectArch()
484 if (!(getSTI().getFeatureBits()[Feature])) { in setFeatureBits()
493 if (getSTI().getFeatureBits()[Feature]) { in clearFeatureBits()
603 return getSTI().getFeatureBits()[Mips::FeatureFPXX]; in isABI_FPXX()
615 return getSTI().getFeatureBits()[Mips::FeatureMips1]; in hasMips1()
675 return getSTI().getFeatureBits()[Mips::FeatureDSP]; in hasDSP()
687 return getSTI().getFeatureBits()[Mips::FeatureMSA]; in hasMSA()
714 return getSTI().getFeatureBits()[Mips::FeatureMT]; in hasMT()
718 return getSTI().getFeatureBits()[Mips::FeatureCRC]; in hasCRC()
722 return getSTI().getFeatureBits()[Mips::FeatureVirt]; in hasVirt()
[all …]
/llvm-project-15.0.7/llvm/lib/Target/AMDGPU/
H A DR600MCInstLower.cpp47 getSubtargetInfo().getFeatureBits()); in emitInstruction()
/llvm-project-15.0.7/llvm/lib/Target/RISCV/AsmParser/
H A DRISCVAsmParser.cpp183 if (!(getSTI().getFeatureBits()[Feature])) { in setFeatureBits()
190 bool getFeatureBits(uint64_t Feature) { in getFeatureBits() function in __anon4b8be85e0111::RISCVAsmParser
191 return getSTI().getFeatureBits()[Feature]; in getFeatureBits()
195 if (getSTI().getFeatureBits()[Feature]) { in clearFeatureBits()
205 FeatureBitStack.push_back(getSTI().getFeatureBits()); in pushFeatureBits()
244 setAvailableFeatures(ComputeAvailableFeatures(STI.getFeatureBits())); in RISCVAsmParser()
248 !getSTI().getFeatureBits()[RISCV::FeatureStdExtF]) { in RISCVAsmParser()
253 !getSTI().getFeatureBits()[RISCV::FeatureStdExtD]) { in RISCVAsmParser()
1494 if (!SysReg->haveRequiredFeatures(getSTI().getFeatureBits())) { in parseCSRSystemRegister()
1965 if (getSTI().getFeatureBits()[RISCV::FeatureRelax]) { in ParseInstruction()
[all …]
/llvm-project-15.0.7/llvm/lib/Target/AVR/MCTargetDesc/
H A DAVRELFStreamer.cpp63 EFlags |= getEFlagsForFeatureSet(STI.getFeatureBits()); in AVRELFStreamer()

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