145bb48eaSTom Stellard //===-- MCTargetDesc/AMDGPUMCAsmInfo.cpp - Assembly Info ------------------===//
245bb48eaSTom Stellard //
32946cd70SChandler Carruth // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
42946cd70SChandler Carruth // See https://llvm.org/LICENSE.txt for license information.
52946cd70SChandler Carruth // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
645bb48eaSTom Stellard //
745bb48eaSTom Stellard /// \file
845bb48eaSTom Stellard //===----------------------------------------------------------------------===//
945bb48eaSTom Stellard 
1045bb48eaSTom Stellard #include "AMDGPUMCAsmInfo.h"
1101e062f5SMatt Arsenault #include "llvm/ADT/Triple.h"
12ca64ef20SMatt Arsenault #include "llvm/MC/MCSubtargetInfo.h"
13ca64ef20SMatt Arsenault #include "MCTargetDesc/AMDGPUMCTargetDesc.h"
1445bb48eaSTom Stellard 
1545bb48eaSTom Stellard using namespace llvm;
1601e062f5SMatt Arsenault 
AMDGPUMCAsmInfo(const Triple & TT,const MCTargetOptions & Options)174b63ca13SMirko Brkusanin AMDGPUMCAsmInfo::AMDGPUMCAsmInfo(const Triple &TT,
18*f3a344d2SKazu Hirata                                  const MCTargetOptions &Options) {
1912096848SKonstantin Zhuravlyov   CodePointerSize = (TT.getArch() == Triple::amdgcn) ? 8 : 4;
20df6539f4SMatt Arsenault   StackGrowsUp = true;
2145bb48eaSTom Stellard   HasSingleParameterDotFile = false;
2245bb48eaSTom Stellard   //===------------------------------------------------------------------===//
23ed1fd7e0SMatt Arsenault   MinInstAlignment = 4;
24ca64ef20SMatt Arsenault 
25ca64ef20SMatt Arsenault   // This is the maximum instruction encoded size for gfx10. With a known
26ca64ef20SMatt Arsenault   // subtarget, it can be reduced to 8 bytes.
27ca64ef20SMatt Arsenault   MaxInstLength = (TT.getArch() == Triple::amdgcn) ? 20 : 16;
2845bb48eaSTom Stellard   SeparatorString = "\n";
2945bb48eaSTom Stellard   CommentString = ";";
3045bb48eaSTom Stellard   InlineAsmStart = ";#ASMSTART";
3145bb48eaSTom Stellard   InlineAsmEnd = ";#ASMEND";
3245bb48eaSTom Stellard 
3345bb48eaSTom Stellard   //===--- Data Emission Directives -------------------------------------===//
3445bb48eaSTom Stellard   SunStyleELFSectionSwitchSyntax = true;
3545bb48eaSTom Stellard   UsesELFSectionDirectiveForBSS = true;
3645bb48eaSTom Stellard 
3745bb48eaSTom Stellard   //===--- Global Variable Emission Directives --------------------------===//
3845bb48eaSTom Stellard   HasAggressiveSymbolFolding = true;
3945bb48eaSTom Stellard   COMMDirectiveAlignmentIsInBytes = false;
4045bb48eaSTom Stellard   HasNoDeadStrip = true;
4145bb48eaSTom Stellard   //===--- Dwarf Emission Directives -----------------------------------===//
4245bb48eaSTom Stellard   SupportsDebugInformation = true;
4341f8b8e8SRamNalamothu   UsesCFIForDebug = true;
4468f163dfSScott Linder   DwarfRegNumForCFI = true;
45d2e5157cSFangrui Song 
46d2e5157cSFangrui Song   UseIntegratedAssembler = false;
4745bb48eaSTom Stellard }
48e135ffd5STom Stellard 
shouldOmitSectionDirective(StringRef SectionName) const49e135ffd5STom Stellard bool AMDGPUMCAsmInfo::shouldOmitSectionDirective(StringRef SectionName) const {
5000f2f91aSTom Stellard   return SectionName == ".hsatext" || SectionName == ".hsadata_global_agent" ||
5100f2f91aSTom Stellard          SectionName == ".hsadata_global_program" ||
529760f037STom Stellard          SectionName == ".hsarodata_readonly_agent" ||
53e135ffd5STom Stellard          MCAsmInfo::shouldOmitSectionDirective(SectionName);
54e135ffd5STom Stellard }
55ca64ef20SMatt Arsenault 
getMaxInstLength(const MCSubtargetInfo * STI) const56ca64ef20SMatt Arsenault unsigned AMDGPUMCAsmInfo::getMaxInstLength(const MCSubtargetInfo *STI) const {
57ca64ef20SMatt Arsenault   if (!STI || STI->getTargetTriple().getArch() == Triple::r600)
58ca64ef20SMatt Arsenault     return MaxInstLength;
59ca64ef20SMatt Arsenault 
60ca64ef20SMatt Arsenault   // Maximum for NSA encoded images
61ca64ef20SMatt Arsenault   if (STI->getFeatureBits()[AMDGPU::FeatureNSAEncoding])
62ca64ef20SMatt Arsenault     return 20;
63ca64ef20SMatt Arsenault 
64ca64ef20SMatt Arsenault   // 64-bit instruction with 32-bit literal.
65ca64ef20SMatt Arsenault   if (STI->getFeatureBits()[AMDGPU::FeatureVOP3Literal])
66ca64ef20SMatt Arsenault     return 12;
67ca64ef20SMatt Arsenault 
68ca64ef20SMatt Arsenault   return 8;
69ca64ef20SMatt Arsenault }
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