1 //===-- RISCVAsmPrinter.cpp - RISCV LLVM assembly writer ------------------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file contains a printer that converts from our internal representation
10 // of machine-dependent LLVM code to the RISCV assembly language.
11 //
12 //===----------------------------------------------------------------------===//
13
14 #include "MCTargetDesc/RISCVInstPrinter.h"
15 #include "MCTargetDesc/RISCVMCExpr.h"
16 #include "MCTargetDesc/RISCVTargetStreamer.h"
17 #include "RISCV.h"
18 #include "RISCVTargetMachine.h"
19 #include "TargetInfo/RISCVTargetInfo.h"
20 #include "llvm/ADT/Statistic.h"
21 #include "llvm/CodeGen/AsmPrinter.h"
22 #include "llvm/CodeGen/MachineConstantPool.h"
23 #include "llvm/CodeGen/MachineFunctionPass.h"
24 #include "llvm/CodeGen/MachineInstr.h"
25 #include "llvm/CodeGen/MachineModuleInfo.h"
26 #include "llvm/MC/MCAsmInfo.h"
27 #include "llvm/MC/MCInst.h"
28 #include "llvm/MC/MCStreamer.h"
29 #include "llvm/MC/MCSymbol.h"
30 #include "llvm/MC/TargetRegistry.h"
31 #include "llvm/Support/raw_ostream.h"
32 using namespace llvm;
33
34 #define DEBUG_TYPE "asm-printer"
35
36 STATISTIC(RISCVNumInstrsCompressed,
37 "Number of RISC-V Compressed instructions emitted");
38
39 namespace {
40 class RISCVAsmPrinter : public AsmPrinter {
41 const MCSubtargetInfo *MCSTI;
42 const RISCVSubtarget *STI;
43
44 public:
RISCVAsmPrinter(TargetMachine & TM,std::unique_ptr<MCStreamer> Streamer)45 explicit RISCVAsmPrinter(TargetMachine &TM,
46 std::unique_ptr<MCStreamer> Streamer)
47 : AsmPrinter(TM, std::move(Streamer)), MCSTI(TM.getMCSubtargetInfo()) {}
48
getPassName() const49 StringRef getPassName() const override { return "RISCV Assembly Printer"; }
50
51 bool runOnMachineFunction(MachineFunction &MF) override;
52
53 void emitInstruction(const MachineInstr *MI) override;
54
55 bool PrintAsmOperand(const MachineInstr *MI, unsigned OpNo,
56 const char *ExtraCode, raw_ostream &OS) override;
57 bool PrintAsmMemoryOperand(const MachineInstr *MI, unsigned OpNo,
58 const char *ExtraCode, raw_ostream &OS) override;
59
60 void EmitToStreamer(MCStreamer &S, const MCInst &Inst);
61 bool emitPseudoExpansionLowering(MCStreamer &OutStreamer,
62 const MachineInstr *MI);
63
64 // Wrapper needed for tblgenned pseudo lowering.
lowerOperand(const MachineOperand & MO,MCOperand & MCOp) const65 bool lowerOperand(const MachineOperand &MO, MCOperand &MCOp) const {
66 return lowerRISCVMachineOperandToMCOperand(MO, MCOp, *this);
67 }
68
69 void emitStartOfAsmFile(Module &M) override;
70 void emitEndOfAsmFile(Module &M) override;
71
72 void emitFunctionEntryLabel() override;
73
74 private:
75 void emitAttributes();
76 };
77 }
78
79 #define GEN_COMPRESS_INSTR
80 #include "RISCVGenCompressInstEmitter.inc"
EmitToStreamer(MCStreamer & S,const MCInst & Inst)81 void RISCVAsmPrinter::EmitToStreamer(MCStreamer &S, const MCInst &Inst) {
82 MCInst CInst;
83 bool Res = compressInst(CInst, Inst, *STI, OutStreamer->getContext());
84 if (Res)
85 ++RISCVNumInstrsCompressed;
86 AsmPrinter::EmitToStreamer(*OutStreamer, Res ? CInst : Inst);
87 }
88
89 // Simple pseudo-instructions have their lowering (with expansion to real
90 // instructions) auto-generated.
91 #include "RISCVGenMCPseudoLowering.inc"
92
emitInstruction(const MachineInstr * MI)93 void RISCVAsmPrinter::emitInstruction(const MachineInstr *MI) {
94 RISCV_MC::verifyInstructionPredicates(MI->getOpcode(),
95 getSubtargetInfo().getFeatureBits());
96
97 // Do any auto-generated pseudo lowerings.
98 if (emitPseudoExpansionLowering(*OutStreamer, MI))
99 return;
100
101 MCInst TmpInst;
102 if (!lowerRISCVMachineInstrToMCInst(MI, TmpInst, *this))
103 EmitToStreamer(*OutStreamer, TmpInst);
104 }
105
PrintAsmOperand(const MachineInstr * MI,unsigned OpNo,const char * ExtraCode,raw_ostream & OS)106 bool RISCVAsmPrinter::PrintAsmOperand(const MachineInstr *MI, unsigned OpNo,
107 const char *ExtraCode, raw_ostream &OS) {
108 // First try the generic code, which knows about modifiers like 'c' and 'n'.
109 if (!AsmPrinter::PrintAsmOperand(MI, OpNo, ExtraCode, OS))
110 return false;
111
112 const MachineOperand &MO = MI->getOperand(OpNo);
113 if (ExtraCode && ExtraCode[0]) {
114 if (ExtraCode[1] != 0)
115 return true; // Unknown modifier.
116
117 switch (ExtraCode[0]) {
118 default:
119 return true; // Unknown modifier.
120 case 'z': // Print zero register if zero, regular printing otherwise.
121 if (MO.isImm() && MO.getImm() == 0) {
122 OS << RISCVInstPrinter::getRegisterName(RISCV::X0);
123 return false;
124 }
125 break;
126 case 'i': // Literal 'i' if operand is not a register.
127 if (!MO.isReg())
128 OS << 'i';
129 return false;
130 }
131 }
132
133 switch (MO.getType()) {
134 case MachineOperand::MO_Immediate:
135 OS << MO.getImm();
136 return false;
137 case MachineOperand::MO_Register:
138 OS << RISCVInstPrinter::getRegisterName(MO.getReg());
139 return false;
140 case MachineOperand::MO_GlobalAddress:
141 PrintSymbolOperand(MO, OS);
142 return false;
143 case MachineOperand::MO_BlockAddress: {
144 MCSymbol *Sym = GetBlockAddressSymbol(MO.getBlockAddress());
145 Sym->print(OS, MAI);
146 return false;
147 }
148 default:
149 break;
150 }
151
152 return true;
153 }
154
PrintAsmMemoryOperand(const MachineInstr * MI,unsigned OpNo,const char * ExtraCode,raw_ostream & OS)155 bool RISCVAsmPrinter::PrintAsmMemoryOperand(const MachineInstr *MI,
156 unsigned OpNo,
157 const char *ExtraCode,
158 raw_ostream &OS) {
159 if (!ExtraCode) {
160 const MachineOperand &MO = MI->getOperand(OpNo);
161 // For now, we only support register memory operands in registers and
162 // assume there is no addend
163 if (!MO.isReg())
164 return true;
165
166 OS << "0(" << RISCVInstPrinter::getRegisterName(MO.getReg()) << ")";
167 return false;
168 }
169
170 return AsmPrinter::PrintAsmMemoryOperand(MI, OpNo, ExtraCode, OS);
171 }
172
runOnMachineFunction(MachineFunction & MF)173 bool RISCVAsmPrinter::runOnMachineFunction(MachineFunction &MF) {
174 // Set the current MCSubtargetInfo to a copy which has the correct
175 // feature bits for the current MachineFunction
176 MCSubtargetInfo &NewSTI =
177 OutStreamer->getContext().getSubtargetCopy(*TM.getMCSubtargetInfo());
178 NewSTI.setFeatureBits(MF.getSubtarget().getFeatureBits());
179 MCSTI = &NewSTI;
180 STI = &MF.getSubtarget<RISCVSubtarget>();
181
182 SetupMachineFunction(MF);
183 emitFunctionBody();
184 return false;
185 }
186
emitStartOfAsmFile(Module & M)187 void RISCVAsmPrinter::emitStartOfAsmFile(Module &M) {
188 if (TM.getTargetTriple().isOSBinFormatELF())
189 emitAttributes();
190 }
191
emitEndOfAsmFile(Module & M)192 void RISCVAsmPrinter::emitEndOfAsmFile(Module &M) {
193 RISCVTargetStreamer &RTS =
194 static_cast<RISCVTargetStreamer &>(*OutStreamer->getTargetStreamer());
195
196 if (TM.getTargetTriple().isOSBinFormatELF())
197 RTS.finishAttributeSection();
198 }
199
emitAttributes()200 void RISCVAsmPrinter::emitAttributes() {
201 RISCVTargetStreamer &RTS =
202 static_cast<RISCVTargetStreamer &>(*OutStreamer->getTargetStreamer());
203 RTS.emitTargetAttributes(*MCSTI);
204 }
205
emitFunctionEntryLabel()206 void RISCVAsmPrinter::emitFunctionEntryLabel() {
207 AsmPrinter::emitFunctionEntryLabel();
208 RISCVTargetStreamer &RTS =
209 static_cast<RISCVTargetStreamer &>(*OutStreamer->getTargetStreamer());
210 RTS.setTargetABI(STI->getTargetABI());
211 }
212
213 // Force static initialization.
LLVMInitializeRISCVAsmPrinter()214 extern "C" LLVM_EXTERNAL_VISIBILITY void LLVMInitializeRISCVAsmPrinter() {
215 RegisterAsmPrinter<RISCVAsmPrinter> X(getTheRISCV32Target());
216 RegisterAsmPrinter<RISCVAsmPrinter> Y(getTheRISCV64Target());
217 }
218