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Searched refs:getDefRegState (Results 1 – 20 of 20) sorted by relevance

/llvm-project-15.0.7/llvm/lib/Target/MSP430/
H A DMSP430InstrInfo.cpp80 .addReg(DestReg, getDefRegState(true)).addFrameIndex(FrameIdx) in loadRegFromStackSlot()
84 .addReg(DestReg, getDefRegState(true)).addFrameIndex(FrameIdx) in loadRegFromStackSlot()
/llvm-project-15.0.7/llvm/lib/Target/ARM/
H A DThumb1InstrInfo.cpp74 .addReg(DestReg, getDefRegState(true)); in copyPhysReg()
H A DThumbRegisterInfo.cpp76 .addReg(DestReg, getDefRegState(true), SubIdx) in emitThumb1LoadConstPool()
95 .addReg(DestReg, getDefRegState(true), SubIdx) in emitThumb2LoadConstPool()
H A DARMLoadStoreOptimizer.cpp811 MIB.addReg(Base, getDefRegState(true)) in CreateLoadStoreMulti()
827 MIB.addReg(R.first, getDefRegState(isDef) | getKillRegState(R.second)); in CreateLoadStoreMulti()
1350 .addReg(Base, getDefRegState(true)) // WB base register in MergeBaseUpdateLSMultiple()
1531 .addReg(Base, getDefRegState(true)) // WB base register in MergeBaseUpdateLoadStore()
1535 .addReg(MO.getReg(), (isLd ? getDefRegState(true) in MergeBaseUpdateLoadStore()
1742 .addReg(Reg, getDefRegState(true) | getDeadRegState(RegDeadKill)) in InsertLDR_STR()
1813 .addReg(EvenReg, getDefRegState(isLd) | getDeadRegState(EvenDeadKill)) in FixInvalidRegPairOp()
1814 .addReg(OddReg, getDefRegState(isLd) | getDeadRegState(OddDeadKill)) in FixInvalidRegPairOp()
H A DMLxExpansionPass.cpp298 .addReg(DstReg, getDefRegState(true) | getDeadRegState(DstDead)); in ExpandFPMLxInstruction()
H A DARMBaseRegisterInfo.cpp508 .addReg(DestReg, getDefRegState(true), SubIdx) in emitLoadConstPool()
H A DThumb1FrameLowering.cpp1080 MIB.addReg(Reg, getDefRegState(true)); in popRegsFromStack()
H A DARMFrameLowering.cpp1650 MIB.addReg(Regs[i], getDefRegState(true)); in emitPopInst()
H A DARMExpandPseudoInsts.cpp902 getDefRegState(MI.getOperand(0).isDef()); in ExpandMQQPRLoadStore()
/llvm-project-15.0.7/llvm/lib/Target/AArch64/
H A DAArch64LowerHomogeneousPrologEpilog.cpp235 MIB.addReg(Reg2, getDefRegState(true)) in emitLoad()
236 .addReg(Reg1, getDefRegState(true)) in emitLoad()
H A DAArch64FrameLowering.cpp2892 MIB.addReg(Reg2, getDefRegState(true)); in restoreCalleeSavedRegisters()
2897 MIB.addReg(Reg1, getDefRegState(true)) in restoreCalleeSavedRegisters()
H A DAArch64InstrInfo.cpp4058 .addReg(DestReg, getDefRegState(true)) in loadRegFromStackSlot()
/llvm-project-15.0.7/llvm/include/llvm/CodeGen/
H A DMachineInstrBuilder.h502 inline unsigned getDefRegState(bool B) { in getDefRegState() function
530 return getDefRegState(RegOp.isDef()) | getImplRegState(RegOp.isImplicit()) | in getRegState()
/llvm-project-15.0.7/llvm/lib/Target/Lanai/
H A DLanaiMemAluCombiner.cpp260 InstrBuilder.addReg(Dest.getReg(), getDefRegState(true)); in insertMergedInstruction()
/llvm-project-15.0.7/llvm/lib/CodeGen/
H A DMachineInstrBundle.cpp219 MIB.addReg(Reg, getDefRegState(true) | getDeadRegState(isDead) | in finalizeBundle()
/llvm-project-15.0.7/llvm/lib/Target/AMDGPU/
H A DSIFixSGPRCopies.cpp633 .addReg(Tmp, getDefRegState(true)) in runOnMachineFunction()
H A DSIRegisterInfo.cpp1489 unsigned SrcDstRegState = getDefRegState(!IsStore); in buildSpillLoadStore()
1583 .addReg(SubReg, getDefRegState(!IsStore) | getKillRegState(IsKill)); in buildSpillLoadStore()
/llvm-project-15.0.7/llvm/lib/CodeGen/SelectionDAG/
H A DInstrEmitter.cpp365 MIB.addReg(VReg, getDefRegState(isOptDef) | getKillRegState(isKill) | in AddRegisterOperand()
/llvm-project-15.0.7/llvm/lib/Target/X86/
H A DX86FrameLowering.cpp313 .addReg(Reg, getDefRegState(!isSub) | getUndefRegState(isSub)) in emitSPUpdate()
H A DX86InstrInfo.cpp6933 getDefRegState(ImpOp.isDef()) | in unfoldMemoryOperand()