| /llvm-project-15.0.7/llvm/include/llvm/CodeGen/ |
| H A D | MachineInstr.h | 1375 return findRegisterDefOperandIdx(Reg, false, false, TRI) != -1;
1383 return findRegisterDefOperandIdx(Reg, false, true, TRI) != -1;
1391 return findRegisterDefOperandIdx(Reg, true, false, TRI) != -1;
1425 int findRegisterDefOperandIdx(Register Reg,
1435 int Idx = findRegisterDefOperandIdx(Reg, isDead, Overlap, TRI);
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| /llvm-project-15.0.7/llvm/lib/Target/AArch64/GISel/ |
| H A D | AArch64PostSelectOptimize.cpp | 144 int DeadNZCVIdx = II.findRegisterDefOperandIdx(AArch64::NZCV); in optimizeNZCVDefs()
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| /llvm-project-15.0.7/llvm/lib/CodeGen/ |
| H A D | MachineCombiner.cpp | 237 int DefIdx = DefInstr->findRegisterDefOperandIdx(MO.getReg()); in getDepth()
247 DefInstr, DefInstr->findRegisterDefOperandIdx(MO.getReg()), in getDepth()
291 NewRoot, NewRoot->findRegisterDefOperandIdx(MO.getReg()), UseMO, in getLatency()
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| H A D | EarlyIfConversion.cpp | 596 int TIdx = TDef->findRegisterDefOperandIdx(TReg); in hasSameValue()
597 int FIdx = FDef->findRegisterDefOperandIdx(FReg); in hasSameValue()
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| H A D | AggressiveAntiDepBreaker.cpp | 691 int Idx = UseMI->findRegisterDefOperandIdx(NewReg, false, true, TRI); in FindSuitableFreeRegisters()
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| H A D | ModuloSchedule.cpp | 1660 assert(Def->findRegisterDefOperandIdx(MI.getOperand(1).getReg()) != -1); in moveStageBetweenBlocks()
1886 unsigned OpIdx = MI->findRegisterDefOperandIdx(Reg); in getEquivalentRegisterIn()
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| H A D | TwoAddressInstructionPass.cpp | 1330 unsigned NewDstIdx = NewMIs[1]->findRegisterDefOperandIdx(regA); in tryInstructionTransform()
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| H A D | MachineInstr.cpp | 994 MachineInstr::findRegisterDefOperandIdx(Register Reg, bool isDead, bool Overlap, in findRegisterDefOperandIdx() function in MachineInstr
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| H A D | RegisterCoalescer.cpp | 861 int DefIdx = DefMI->findRegisterDefOperandIdx(IntA.reg()); in removeCopyByCommutingDef()
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| /llvm-project-15.0.7/llvm/lib/Target/AArch64/ |
| H A D | AArch64InstrInfo.cpp | 549 if (DefMI->findRegisterDefOperandIdx(AArch64::NZCV, true) == -1) in canFoldIntoCSel()
577 if (DefMI->findRegisterDefOperandIdx(AArch64::NZCV, true) == -1) in canFoldIntoCSel()
1429 int DeadNZCVIdx = CmpInstr.findRegisterDefOperandIdx(AArch64::NZCV, true); in optimizeCompareInstr()
1738 if (MI.findRegisterDefOperandIdx(AArch64::NZCV, true) != -1) in canCmpInstrBeRemoved()
4870 MI->findRegisterDefOperandIdx(AArch64::NZCV, true) == -1) in canCombine()
4928 int Cmp_NZCV = Root.findRegisterDefOperandIdx(AArch64::NZCV, true); in getMaddPatterns()
5394 Root.findRegisterDefOperandIdx(AArch64::NZCV, true) == -1) in getMiscPatterns()
6779 if (DefMI->findRegisterDefOperandIdx(AArch64::NZCV, true) != -1) in optimizeCondBranch()
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| /llvm-project-15.0.7/llvm/lib/Target/AMDGPU/ |
| H A D | R600InstrInfo.cpp | 214 return MI.findRegisterDefOperandIdx(R600::AR_X, false, false, &RI) != -1; in definesAddressRegister()
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| H A D | SIInstrInfo.cpp | 6326 int SCCIdx = Inst.findRegisterDefOperandIdx(AMDGPU::SCC); in moveToVALU()
6518 if (CandI.findRegisterDefOperandIdx(AMDGPU::SCC, false, false, &RI) != in lowerSelect()
7181 if (MI.findRegisterDefOperandIdx(AMDGPU::SCC, false, false, &RI) != -1) in addSCCDefUsersToVALUWorklist()
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| /llvm-project-15.0.7/llvm/lib/Target/ARM/ |
| H A D | ARMLowOverheadLoops.cpp | 90 return MI->findRegisterDefOperandIdx(ARM::VPR) != -1; in isVectorPredicate()
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| H A D | ARMBaseInstrInfo.cpp | 1730 int ImpDefIdx = MI.findRegisterDefOperandIdx(DstRegD); in expandPostRAPseudo()
4133 Idx = II->findRegisterDefOperandIdx(Reg, false, true, TRI); in getBundledDefMI()
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| /llvm-project-15.0.7/llvm/lib/CodeGen/GlobalISel/ |
| H A D | CombinerHelper.cpp | 2441 return I1->findRegisterDefOperandIdx(InstAndDef1->Reg) == in matchEqualDefs()
2442 I2->findRegisterDefOperandIdx(InstAndDef2->Reg); in matchEqualDefs()
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| /llvm-project-15.0.7/llvm/lib/Target/Hexagon/ |
| H A D | HexagonInstrInfo.cpp | 4301 int Idx = DefMI.findRegisterDefOperandIdx(*SR, false, false, &HRI); in getOperandLatency()
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