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Searched refs:constrainOperandRegClass (Results 1 – 16 of 16) sorted by relevance

/llvm-project-15.0.7/llvm/lib/Target/ARM/
H A DARMFastISel.cpp304 Op0 = constrainOperandRegClass(II, Op0, 1); in fastEmitInst_r()
326 Op0 = constrainOperandRegClass(II, Op0, 1); in fastEmitInst_rr()
327 Op1 = constrainOperandRegClass(II, Op1, 2); in fastEmitInst_rr()
353 Op0 = constrainOperandRegClass(II, Op0, 1); in fastEmitInst_ri()
1127 SrcReg = constrainOperandRegClass(TII.get(StrOpc), SrcReg, 0); in ARMEmitStore()
1301 CmpReg = constrainOperandRegClass(TII.get(TstOpc), CmpReg, 0); in SelectBranch()
1432 SrcReg1 = constrainOperandRegClass(II, SrcReg1, 0); in ARMEmitCmp()
1434 SrcReg2 = constrainOperandRegClass(II, SrcReg2, 1); in ARMEmitCmp()
1767 SrcReg1 = constrainOperandRegClass(TII.get(Opc), SrcReg1, 1); in SelectBinaryIntOp()
1768 SrcReg2 = constrainOperandRegClass(TII.get(Opc), SrcReg2, 2); in SelectBinaryIntOp()
[all …]
H A DARMCallLowering.cpp485 MIB->getOperand(CalleeIdx).setReg(constrainOperandRegClass( in lowerCall()
/llvm-project-15.0.7/llvm/include/llvm/CodeGen/GlobalISel/
H A DUtils.h102 Register constrainOperandRegClass(const MachineFunction &MF,
121 Register constrainOperandRegClass(const MachineFunction &MF,
H A DInstructionSelectorImpl.h1091 constrainOperandRegClass(MF, TRI, MRI, TII, RBI, I, RC, MO); in executeMatchTable()
/llvm-project-15.0.7/llvm/lib/CodeGen/SelectionDAG/
H A DFastISel.cpp1900 Register FastISel::constrainOperandRegClass(const MCInstrDesc &II, Register Op, in constrainOperandRegClass() function in FastISel
1931 Op0 = constrainOperandRegClass(II, Op0, II.getNumDefs()); in fastEmitInst_r()
1952 Op0 = constrainOperandRegClass(II, Op0, II.getNumDefs()); in fastEmitInst_rr()
1953 Op1 = constrainOperandRegClass(II, Op1, II.getNumDefs() + 1); in fastEmitInst_rr()
1975 Op0 = constrainOperandRegClass(II, Op0, II.getNumDefs()); in fastEmitInst_rrr()
1976 Op1 = constrainOperandRegClass(II, Op1, II.getNumDefs() + 1); in fastEmitInst_rrr()
1977 Op2 = constrainOperandRegClass(II, Op2, II.getNumDefs() + 2); in fastEmitInst_rrr()
2001 Op0 = constrainOperandRegClass(II, Op0, II.getNumDefs()); in fastEmitInst_ri()
2023 Op0 = constrainOperandRegClass(II, Op0, II.getNumDefs()); in fastEmitInst_rii()
2066 Op0 = constrainOperandRegClass(II, Op0, II.getNumDefs()); in fastEmitInst_rri()
[all …]
/llvm-project-15.0.7/llvm/lib/Target/AArch64/GISel/
H A DAArch64PostSelectOptimize.cpp156 constrainOperandRegClass(MF, *TRI, MRI, *TII, *RBI, II, II.getDesc(), in optimizeNZCVDefs()
H A DAArch64CallLowering.cpp1084 constrainOperandRegClass(MF, *TRI, MRI, *MF.getSubtarget().getInstrInfo(), in lowerTailCall()
1211 constrainOperandRegClass(MF, *TRI, MRI, *Subtarget.getInstrInfo(), in lowerCall()
/llvm-project-15.0.7/llvm/lib/Target/AArch64/
H A DAArch64FastISel.cpp1309 LHSReg = constrainOperandRegClass(II, LHSReg, II.getNumDefs()); in emitAddSub_rr()
1354 LHSReg = constrainOperandRegClass(II, LHSReg, II.getNumDefs()); in emitAddSub_ri()
1395 LHSReg = constrainOperandRegClass(II, LHSReg, II.getNumDefs()); in emitAddSub_rs()
2049 SrcReg = constrainOperandRegClass(II, SrcReg, 0); in emitStoreRelease()
2050 AddrReg = constrainOperandRegClass(II, AddrReg, 1); in emitStoreRelease()
2484 = constrainOperandRegClass(II, CondReg, II.getNumDefs()); in selectBranch()
2747 CondReg = constrainOperandRegClass(II, CondReg, 1); in selectSelect()
3246 CallReg = constrainOperandRegClass(II, CallReg, 0); in fastLowerCall()
4993 const Register AddrReg = constrainOperandRegClass( in selectAtomicCmpXchg()
4995 const Register DesiredReg = constrainOperandRegClass( in selectAtomicCmpXchg()
[all …]
/llvm-project-15.0.7/llvm/lib/CodeGen/GlobalISel/
H A DUtils.cpp51 Register llvm::constrainOperandRegClass( in constrainOperandRegClass() function in llvm
103 Register llvm::constrainOperandRegClass( in constrainOperandRegClass() function in llvm
146 return constrainOperandRegClass(MF, TRI, MRI, TII, RBI, InsertPt, *OpRC, in constrainOperandRegClass()
183 constrainOperandRegClass(MF, TRI, MRI, TII, RBI, I, I.getDesc(), MO, OpI); in constrainSelectedInstRegOperands()
/llvm-project-15.0.7/llvm/lib/Target/M68k/GISel/
H A DM68kCallLowering.cpp207 constrainOperandRegClass(MF, *TRI, MRI, *STI.getInstrInfo(), in lowerCall()
/llvm-project-15.0.7/llvm/include/llvm/CodeGen/
H A DFastISel.h470 Register constrainOperandRegClass(const MCInstrDesc &II, Register Op,
/llvm-project-15.0.7/llvm/lib/Target/X86/
H A DX86CallLowering.cpp357 MIB->getOperand(0).setReg(constrainOperandRegClass( in lowerCall()
H A DX86FastISel.cpp217 AM.IndexReg = constrainOperandRegClass(MIB->getDesc(), AM.IndexReg, in addFullAddress()
644 ValReg = constrainOperandRegClass(Desc, ValReg, Desc.getNumOperands() - 1); in X86FastEmitStore()
3962 Register IndexReg = constrainOperandRegClass(Result->getDesc(), in tryToFoldLoadIntoMI()
3983 Op0 = constrainOperandRegClass(II, Op0, II.getNumDefs()); in fastEmitInst_rrrr()
3984 Op1 = constrainOperandRegClass(II, Op1, II.getNumDefs() + 1); in fastEmitInst_rrrr()
3985 Op2 = constrainOperandRegClass(II, Op2, II.getNumDefs() + 2); in fastEmitInst_rrrr()
3986 Op3 = constrainOperandRegClass(II, Op3, II.getNumDefs() + 3); in fastEmitInst_rrrr()
/llvm-project-15.0.7/llvm/lib/Target/AMDGPU/
H A DAMDGPUCallLowering.cpp1280 MIB->getOperand(0).setReg(constrainOperandRegClass( in lowerTailCall()
1391 MIB->getOperand(1).setReg(constrainOperandRegClass( in lowerCall()
H A DAMDGPUInstructionSelector.cpp515 SrcReg = constrainOperandRegClass(*MF, TRI, *MRI, TII, RBI, I, in selectG_EXTRACT()
/llvm-project-15.0.7/llvm/lib/Target/Mips/
H A DMipsFastISel.cpp2128 Op0 = constrainOperandRegClass(II, Op0, II.getNumDefs()); in fastEmitInst_rr()
2129 Op1 = constrainOperandRegClass(II, Op1, II.getNumDefs() + 1); in fastEmitInst_rr()