Lines Matching refs:constrainOperandRegClass

1118       constrainOperandRegClass(II, Addr.getReg(), II.getNumDefs()+Idx));  in addLoadStoreOperands()
1120       constrainOperandRegClass(II, Addr.getOffsetReg(), II.getNumDefs()+Idx+1));  in addLoadStoreOperands()
1309   LHSReg = constrainOperandRegClass(II, LHSReg, II.getNumDefs());  in emitAddSub_rr()
1310   RHSReg = constrainOperandRegClass(II, RHSReg, II.getNumDefs() + 1);  in emitAddSub_rr()
1354   LHSReg = constrainOperandRegClass(II, LHSReg, II.getNumDefs());  in emitAddSub_ri()
1395   LHSReg = constrainOperandRegClass(II, LHSReg, II.getNumDefs());  in emitAddSub_rs()
1396   RHSReg = constrainOperandRegClass(II, RHSReg, II.getNumDefs() + 1);  in emitAddSub_rs()
1439   LHSReg = constrainOperandRegClass(II, LHSReg, II.getNumDefs());  in emitAddSub_rx()
1440   RHSReg = constrainOperandRegClass(II, RHSReg, II.getNumDefs() + 1);  in emitAddSub_rx()
2049   SrcReg = constrainOperandRegClass(II, SrcReg, 0);  in emitStoreRelease()
2050   AddrReg = constrainOperandRegClass(II, AddrReg, 1);  in emitStoreRelease()
2118   SrcReg = constrainOperandRegClass(II, SrcReg, II.getNumDefs());  in emitStore()
2353   SrcReg = constrainOperandRegClass(II, SrcReg,  II.getNumDefs());  in emitCompareAndBranch()
2484     = constrainOperandRegClass(II, CondReg, II.getNumDefs());  in selectBranch()
2502   AddrReg = constrainOperandRegClass(II, AddrReg,  II.getNumDefs());  in selectIndirectBr()
2747     CondReg = constrainOperandRegClass(II, CondReg, 1);  in selectSelect()
3219       Register Reg = constrainOperandRegClass(II, Addr.getReg(), 0);  in fastLowerCall()
3246     CallReg = constrainOperandRegClass(II, CallReg, 0);  in fastLowerCall()
4993   const Register AddrReg = constrainOperandRegClass(  in selectAtomicCmpXchg()
4995   const Register DesiredReg = constrainOperandRegClass(  in selectAtomicCmpXchg()
4997   const Register NewReg = constrainOperandRegClass(  in selectAtomicCmpXchg()