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Searched refs:bitsLT (Results 1 – 25 of 26) sorted by relevance

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/llvm-project-15.0.7/llvm/include/llvm/CodeGen/
H A DValueTypes.h272 bool bitsLT(EVT VT) const { in bitsLT() function
H A DTargetLowering.h4307 return VT.bitsLT(MinVT) ? MinVT : VT; in getTypeForExtReturn()
/llvm-project-15.0.7/llvm/lib/Target/ARM/
H A DARMSelectionDAGInfo.cpp107 else if (Src.getValueType().bitsLT(MVT::i32)) in EmitSpecializedLibcall()
/llvm-project-15.0.7/llvm/lib/CodeGen/
H A DTargetLoweringBase.cpp1136 if (EVT(DestVT).bitsLT(NewVT)) // Value is expanded, e.g. i64 -> i16. in getVectorTypeBreakdownMVT()
1609 if (EVT(DestVT).bitsLT(NewVT)) { // Value is expanded, e.g. i64 -> i16. in getVectorTypeBreakdown()
1677 if (VT.bitsLT(MinVT)) in GetReturnInfo()
H A DCodeGenPrepare.cpp1303 if (SrcVT.bitsLT(DstVT)) return false; in OptimizeNoopCopyExpression()
/llvm-project-15.0.7/llvm/lib/CodeGen/SelectionDAG/
H A DSelectionDAG.cpp2804 if (LegalSVT.bitsLT(SVT)) in getSplatValue()
5192 assert(Operand.getValueType().bitsLT(VT) && in getNode()
5219 assert(Operand.getValueType().bitsLT(VT) && in getNode()
5238 assert(Operand.getValueType().bitsLT(VT) && in getNode()
5257 assert(Operand.getValueType().bitsLT(VT) && in getNode()
5295 .bitsLT(VT.getScalarType())) in getNode()
5703 if (LegalSVT.bitsLT(VT.getScalarType())) in FoldConstantArithmetic()
7134 if (VT.bitsLT(LargestVT)) { in getMemsetStores()
7957 assert(SVT.getScalarType().bitsLT(VT.getScalarType()) && in getTruncStore()
9112 assert(Ops[1].getValueType().bitsLT(VTList.VTs[0]) && in getNode()
[all …]
H A DLegalizeTypesGeneric.cpp225 assert(OldEltVT.bitsLT(OldVT) && "Result type smaller then element type!"); in ExpandRes_EXTRACT_VECTOR_ELT()
H A DLegalizeDAG.cpp1495 MemVT.bitsLT(Node->getOperand(0).getValueType()); in ExpandVectorBuildThroughStack()
1746 (SlotVT.bitsLT(DestVT) && in EmitStackConvert()
1776 assert(SlotVT.bitsLT(DestVT) && "Unknown extension!"); in EmitStackConvert()
3049 if (NewEltVT.bitsLT(EltVT)) { in ExpandNode()
4892 assert(NewEltVT.bitsLT(EltVT) && "not handled"); in PromoteNode()
4925 assert(NewEltVT.bitsLT(EltVT) && "not handled"); in PromoteNode()
4971 assert(NewEltVT.bitsLT(EltVT) && "not handled"); in PromoteNode()
H A DFastISel.cpp392 if (IdxVT.bitsLT(PtrVT)) { in getRegForGEPIndex()
1787 if (DstVT.bitsLT(SrcVT)) in selectOperator()
H A DDAGCombiner.cpp5713 if (LdStMemVT.bitsLT(MemVT)) in isLegalNarrowLdSt()
12274 if (SrcVT.bitsLT(VT) && VT.isVector()) { in visitZERO_EXTEND()
12684 if (AssertVT.bitsLT(BigA_AssertVT)) { in visitAssertExt()
12995 ExtVT.bitsLT(cast<VTSDNode>(N0.getOperand(1))->getVT())) in visitSIGN_EXTEND_INREG()
13195 if (N0.getOperand(0).getValueType().bitsLT(VT)) in visitTRUNCATE()
13212 if (ExtVT.bitsLT(VT)) { in visitTRUNCATE()
13347 if (LN0->isSimple() && LN0->getMemoryVT().bitsLT(VT)) { in visitTRUNCATE()
15828 if (VT.bitsLT(In.getValueType())) in visitFP_EXTEND()
19713 if (ResultVT.bitsLT(VecEltVT)) in scalarizeExtractedVectorLoad()
22784 EVT ScaleVT = SVT.bitsLT(InnerSVT) ? VT : InnerVT; in visitVECTOR_SHUFFLE()
[all …]
H A DSelectionDAGBuilder.cpp255 ValueVT.bitsLT(PartEVT)) { in getCopyFromParts()
268 if (ValueVT.bitsLT(PartEVT)) { in getCopyFromParts()
282 if (ValueVT.bitsLT(Val.getValueType())) in getCopyFromParts()
293 ValueVT.bitsLT(PartEVT)) { in getCopyFromParts()
434 } else if (ValueVT.bitsLT(PartEVT)) { in getCopyFromPartsVector()
H A DLegalizeVectorTypes.cpp510 if (BoolVT.bitsLT(CondVT)) in ScalarizeVecRes_VSELECT()
2728 if (N->getValueType(0).bitsLT( in SplitVectorOperand()
3079 if (N->getValueType(0).bitsLT(EltVT)) { in SplitVecOp_EXTRACT_VECTOR_ELT()
H A DTargetLowering.cpp4510 else if (Op0.getValueType().bitsLT(VT)) in SimplifySetCC()
8806 if (VT.bitsLT(MVT::i32)) { in lowerCmpEqZeroToCtlzSrl()
9428 if (RType.bitsLT(Overflow.getValueType())) in expandMULO()
H A DLegalizeIntegerTypes.cpp5320 if (OpVT.bitsLT(NOutVTElem)) { in PromoteIntRes_BUILD_VECTOR()
/llvm-project-15.0.7/llvm/lib/Target/AMDGPU/
H A DR600ISelLowering.cpp1187 if (MemVT.bitsLT(MVT::i32)) in LowerSTORE()
1305 ExtType != ISD::NON_EXTLOAD && MemVT.bitsLT(MVT::i32)) { in LowerLOAD()
1531 if (VT.bitsLT(MVT::i32)) in allowsMisalignedMemoryAccesses()
H A DSIISelLowering.cpp1696 VT.bitsLT(MemVT)) { in convertArgType()
5051 if (NewVT.bitsLT(MVT::i32)) { in ReplaceNodeResults()
8523 if (VT.bitsLT(Op.getValueType())) in getLoadExtOrTrunc()
/llvm-project-15.0.7/llvm/include/llvm/Support/
H A DMachineValueType.h1163 bool bitsLT(MVT VT) const { in bitsLT() function
/llvm-project-15.0.7/llvm/lib/Target/RISCV/
H A DRISCVISelDAGToDAG.cpp2286 if (EltVT.bitsLT(XLenVT)) in selectVSplatSimmHelper()
H A DRISCVISelLowering.cpp4353 assert(DstEltVT.bitsLT(SrcEltVT) && isPowerOf2_64(DstEltVT.getSizeInBits()) && in lowerVectorTruncLike()
4682 if (OpVT.bitsLT(XLenVT)) { in lowerVectorIntrinsicScalars()
7341 if (VT.bitsLT(XLenVT)) { in ReplaceNodeResults()
9149 (IsIndexSigned && IndexVT.getVectorElementType().bitsLT(XLenVT)); in PerformDAGCombine()
9159 if (IndexVT.getVectorElementType().bitsLT(XLenVT)) { in PerformDAGCombine()
/llvm-project-15.0.7/llvm/lib/Target/Mips/
H A DMips64InstrInfo.td71 return cast<VTSDNode>(N->getOperand(1))->getVT().bitsLT(MVT::i32);
H A DMipsISelLowering.cpp4044 return VT.bitsLT(MinVT) ? MinVT : VT; in getTypeForExtReturn()
/llvm-project-15.0.7/llvm/lib/Target/X86/
H A DX86FastISel.cpp3627 if (DstVT.bitsLT(SrcVT)) in fastSelectInstruction()
H A DX86ISelLowering.cpp3337 return VT.bitsLT(MinVT) ? MinVT : VT; in getTypeForExtReturn()
23254 if (Sign.getSimpleValueType().bitsLT(VT)) in LowerFCOPYSIGN()
53512 if (OutVT16.bitsLT(In0.getValueType())) { in matchPMADDWD_2()
53516 if (OutVT16.bitsLT(In1.getValueType())) { in matchPMADDWD_2()
/llvm-project-15.0.7/llvm/lib/Target/AArch64/
H A DAArch64FastISel.cpp4884 if (IdxVT.bitsLT(PtrVT)) { in getRegForGEPIndex()
H A DAArch64ISelLowering.cpp7732 if (SrcVT.bitsLT(VT)) in LowerFCOPYSIGN()
9490 if (SrcEltTy.bitsLT(SmallestEltTy)) { in ReconstructShuffle()

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