| /llvm-project-15.0.7/llvm/lib/Target/AMDGPU/AsmParser/ |
| H A D | AMDGPUAsmParser.cpp | 953 addRegOperands(Inst, N); in addBoolRegOperands()
958 addRegOperands(Inst, N); in addRegOrImmOperands()
969 addRegOperands(Inst, N); in addRegOrImmWithInputModsOperands()
989 addRegOperands(Inst, N); in addRegWithInputModsOperands()
6285 Op.addRegOperands(Inst, 1); in cvtDSOffset01()
6310 Op.addRegOperands(Inst, 1); in cvtDSImpl()
6348 Op.addRegOperands(Inst, 1); in cvtExp()
7619 Op.addRegOperands(Inst, 1); in cvtMubufImpl()
7662 Op.addRegOperands(Inst, 1); in cvtMtbuf()
7716 Op.addRegOperands(Inst, 1); in cvtMIMG()
[all …]
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| /llvm-project-15.0.7/llvm/lib/Target/AArch64/ |
| H A D | AArch64RegisterInfo.td | 183 let RenderMethod = "addRegOperands";
656 let RenderMethod = "addRegOperands";
705 let RenderMethod = "addRegOperands", ParserMethod="tryParseGPRSeqPair" in {
741 let RenderMethod = "addRegOperands";
887 let RenderMethod = "addRegOperands";
930 let RenderMethod = "addRegOperands";
1089 let RenderMethod = "addRegOperands";
1147 let RenderMethod = "addRegOperands";
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| /llvm-project-15.0.7/llvm/lib/Target/M68k/AsmParser/ |
| H A D | M68kAsmParser.cpp | 162 void addRegOperands(MCInst &Inst, unsigned N) const;
309 void M68kOperand::addRegOperands(MCInst &Inst, unsigned N) const { in addRegOperands() function in M68kOperand
|
| /llvm-project-15.0.7/llvm/lib/Target/BPF/AsmParser/ |
| H A D | BPFAsmParser.cpp | 189 void addRegOperands(MCInst &Inst, unsigned N) const { in addRegOperands() function
|
| /llvm-project-15.0.7/llvm/lib/Target/RISCV/ |
| H A D | RISCVInstrInfoD.td | 37 let RenderMethod = "addRegOperands";
43 let RenderMethod = "addRegOperands";
|
| H A D | RISCVInstrInfoF.td | 69 let RenderMethod = "addRegOperands";
|
| H A D | RISCVInstrInfo.td | 126 let RenderMethod = "addRegOperands";
|
| H A D | RISCVInstrInfoV.td | 38 let RenderMethod = "addRegOperands";
|
| /llvm-project-15.0.7/llvm/lib/Target/LoongArch/AsmParser/ |
| H A D | LoongArchAsmParser.cpp | 242 void addRegOperands(MCInst &Inst, unsigned N) const { in addRegOperands() function in __anon1ba74a0a0111::LoongArchOperand
|
| /llvm-project-15.0.7/llvm/lib/Target/MSP430/AsmParser/ |
| H A D | MSP430AsmParser.cpp | 127 void addRegOperands(MCInst &Inst, unsigned N) const { in addRegOperands() function in __anon37a612fe0111::MSP430Operand
|
| /llvm-project-15.0.7/llvm/lib/Target/SystemZ/AsmParser/ |
| H A D | SystemZAsmParser.cpp | 299 void addRegOperands(MCInst &Inst, unsigned N) const { in addRegOperands() function in __anon4f8b82ce0111::SystemZOperand
1320 ZOperand.addRegOperands(Inst, 1); in ParseDirectiveInsn()
|
| /llvm-project-15.0.7/llvm/lib/Target/X86/AsmParser/ |
| H A D | X86Operand.h | 535 void addRegOperands(MCInst &Inst, unsigned N) const { in addRegOperands() function
|
| /llvm-project-15.0.7/llvm/lib/Target/AVR/AsmParser/ |
| H A D | AVRAsmParser.cpp | 134 void addRegOperands(MCInst &Inst, unsigned N) const { in addRegOperands() function in __anonc58108e20111::AVROperand
|
| /llvm-project-15.0.7/llvm/lib/Target/SystemZ/ |
| H A D | SystemZRegisterInfo.td | 41 let RenderMethod = "addRegOperands";
|
| /llvm-project-15.0.7/llvm/lib/Target/WebAssembly/AsmParser/ |
| H A D | WebAssemblyAsmParser.cpp | 118 void addRegOperands(MCInst &, unsigned) const { in addRegOperands() function
|
| /llvm-project-15.0.7/llvm/lib/Target/Lanai/AsmParser/ |
| H A D | LanaiAsmParser.cpp | 402 void addRegOperands(MCInst &Inst, unsigned N) const { in addRegOperands() function
|
| /llvm-project-15.0.7/llvm/lib/Target/MSP430/ |
| H A D | MSP430InstrInfo.td | 96 let RenderMethod = "addRegOperands";
108 let RenderMethod = "addRegOperands";
|
| /llvm-project-15.0.7/llvm/lib/Target/Sparc/AsmParser/ |
| H A D | SparcAsmParser.cpp | 379 void addRegOperands(MCInst &Inst, unsigned N) const { in addRegOperands() function in __anon07e578c20211::SparcOperand
|
| /llvm-project-15.0.7/llvm/lib/Target/VE/AsmParser/ |
| H A D | VEAsmParser.cpp | 465 void addRegOperands(MCInst &Inst, unsigned N) const { in addRegOperands() function in __anone15613a60211::VEOperand
|
| /llvm-project-15.0.7/llvm/lib/Target/CSKY/AsmParser/ |
| H A D | CSKYAsmParser.cpp | 560 void addRegOperands(MCInst &Inst, unsigned N) const { in addRegOperands() function
|
| /llvm-project-15.0.7/llvm/lib/Target/M68k/ |
| H A D | M68kInstrInfo.td | 181 let RenderMethod = "addRegOperands", SuperClasses = [MxRegClass]in {
|
| /llvm-project-15.0.7/llvm/lib/Target/PowerPC/AsmParser/ |
| H A D | PPCAsmParser.cpp | 417 void addRegOperands(MCInst &Inst, unsigned N) const { in addRegOperands() function
|
| /llvm-project-15.0.7/llvm/lib/Target/ARM/AsmParser/ |
| H A D | ARMAsmParser.cpp | 2550 void addRegOperands(MCInst &Inst, unsigned N) const { in addRegOperands() function in __anon2aa686d00111::ARMOperand
5757 ((ARMOperand &)*Operands[3]).addRegOperands(Inst, 1); in cvtThumbMultiply()
5766 ((ARMOperand &)*Operands[RegOp]).addRegOperands(Inst, 1); in cvtThumbMultiply()
5835 ((ARMOperand &)*Operands[2]).addRegOperands(Inst, 1); // Rt in cvtMVEVMOVQtoDReg()
5836 ((ARMOperand &)*Operands[3]).addRegOperands(Inst, 1); // Rt2 in cvtMVEVMOVQtoDReg()
5837 ((ARMOperand &)*Operands[4]).addRegOperands(Inst, 1); // Qd in cvtMVEVMOVQtoDReg()
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| /llvm-project-15.0.7/llvm/lib/Target/Hexagon/AsmParser/ |
| H A D | HexagonAsmParser.cpp | 371 void addRegOperands(MCInst &Inst, unsigned N) const { in addRegOperands() function
|
| /llvm-project-15.0.7/llvm/lib/Target/RISCV/AsmParser/ |
| H A D | RISCVAsmParser.cpp | 903 void addRegOperands(MCInst &Inst, unsigned N) const { in addRegOperands() function
|