[MC] Change EndOfStatement "unexpected tokens in .xxx directive " to "expected newline"

[CSKY] Correct the alignment of FPR register

The alignment of FPR64 and sFPR64 declared in RegisterClass should be 32 bit.

[CSKY] Enhance asm parser and relocation fixup for some special symbol address instruction

Add processing of parsing and emiting lrw/jsri/jmpi instruction, including related fixup and relocation.
Ad

[CSKY] Enhance asm parser and relocation fixup for some special symbol address instruction

Add processing of parsing and emiting lrw/jsri/jmpi instruction, including related fixup and relocation.
Add relax support about pseudo instructions such as jbr/jbsr.
Add objdump format support like arm in llvm-objdump.

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[CSKY] Enable TargetAsmStreamer/ELFStreamer and support asm directive of csky_attribute

Add support of parsing .csky_attribute directive and emit related target attributes in .csky.attribute section

[CSKY] Enable TargetAsmStreamer/ELFStreamer and support asm directive of csky_attribute

Add support of parsing .csky_attribute directive and emit related target attributes in .csky.attribute section.
It does not emit attribute directive in assembly code, so only emit target attributes in ELF streamer.
In ELF streamer, it handles the header EFlag and the csky_attribute section which contains some attribute items.
The EFlag and attribute items are calculated from feature bits based on Subtarget.

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[Support] Add CSKY target parser and attributes parser

Construct LLVM Support module about CSKY target parser and attribute parser.
It refers CSKY ABIv2 and implementation of GNU binutils and GCC.

[Support] Add CSKY target parser and attributes parser

Construct LLVM Support module about CSKY target parser and attribute parser.
It refers CSKY ABIv2 and implementation of GNU binutils and GCC.

https://github.com/c-sky/csky-doc/blob/master/C-SKY_V2_CPU_Applications_Binary_Interface_Standards_Manual.pdf

Now we only support CSKY 800 series cpus and newer cpus in the future undering CSKYv2 ABI specification.
There are 11 archs including ck801, ck802, ck803, ck803s, ck804, ck805, ck807, ck810, ck810v, ck860, ck860v.

Every arch has base extensions, the cpus of that arch family have more extended extensions than base extensions.
We need specify extended extensions for every cpu. Every extension has its enum value, name and related llvm feature string with +/-.
Every enum value represents a bit of uint64_t integer.

Differential Revision: https://reviews.llvm.org/D119917

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[CSKY] Add missing header include in cpp files because of LLVM headers refactor work

[CSKY] Add inline asm constraints and related codegen support

There are kinds of inline asm constraints and corresponding register class or register as following.

'b': mGPRRegClass
'v': sGPRRegCl

[CSKY] Add inline asm constraints and related codegen support

There are kinds of inline asm constraints and corresponding register class or register as following.

'b': mGPRRegClass
'v': sGPRRegClass
'w': sFPR32RegClass or sFPR64RegClass
'c': C register
'z': R14 register
'h': HI register
'l': LO register
'y': HI or LO register

It also adds codegen test for inline-asm including constraints, clobbers and abi names.

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[CSKY] Add floating operation support including float and double

CSKY arch has multiple FPU instruction versions such as FPU, FPUv2 and FPUv3 to implement floating operations.
For now, we just only

[CSKY] Add floating operation support including float and double

CSKY arch has multiple FPU instruction versions such as FPU, FPUv2 and FPUv3 to implement floating operations.
For now, we just only support FPUv2 and FPUv3.

It includes the encoding, asm parsing of instructions and codegen of DAG nodes.

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[CSKY] Add compressed instruction mapping between 32-bit and 16-bit instruction

Add all CompressPat to map instructions between 16-bit and 32-bit with using the CompressInstEmitter infra.
Although i

[CSKY] Add compressed instruction mapping between 32-bit and 16-bit instruction

Add all CompressPat to map instructions between 16-bit and 32-bit with using the CompressInstEmitter infra.
Although it's only used in asm printer, also enable it in asm parser to debug mapping when -enable-csky-asm-compressed-inst is on.

Differential Revision: https://reviews.llvm.org/D115026

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[CSKY] Add CSKY 16-bit instruction format and encoding

CSKY is a ARCH which supports mixture of 16-bit and 32-bit instructions natively,
and there is not an indivual predictor or feature to enable/d

[CSKY] Add CSKY 16-bit instruction format and encoding

CSKY is a ARCH which supports mixture of 16-bit and 32-bit instructions natively,
and there is not an indivual predictor or feature to enable/disable 16-bit instruction.
So I think it's better to add 16-bit instruction early, and naturally to use 16-bit and 32-bit instructions.

Differential Revision: https://reviews.llvm.org/D112919

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Ensure newlines at the end of files (NFC)

[CSKY] Complete to add basic integer instruction set

Complete the basic integer instruction set and add related predictor in CSKY.td.
And it includes the instruction definition and asm parser suppor

[CSKY] Complete to add basic integer instruction set

Complete the basic integer instruction set and add related predictor in CSKY.td.
And it includes the instruction definition and asm parser support.

Differential Revision: https://reviews.llvm.org/D111701

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Move TargetRegistry.(h|cpp) from Support to MC

This moves the registry higher in the LLVM library dependency stack.
Every client of the target registry needs to link against MC anyway to
actually us

Move TargetRegistry.(h|cpp) from Support to MC

This moves the registry higher in the LLVM library dependency stack.
Every client of the target registry needs to link against MC anyway to
actually use the target, so we might as well move this out of Support.

This allows us to ensure that Support doesn't have includes from MC/*.

Differential Revision: https://reviews.llvm.org/D111454

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[llvm][clang][NFC] updates inline licence info

Some files still contained the old University of Illinois Open Source
Licence header. This patch replaces that with the Apache 2 with LLVM
Exception li

[llvm][clang][NFC] updates inline licence info

Some files still contained the old University of Illinois Open Source
Licence header. This patch replaces that with the Apache 2 with LLVM
Exception licence.

Differential Revision: https://reviews.llvm.org/D107528

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[CSKY 6/n] Add support branch and symbol series instruction

This patch adds basic CSKY branch instructions and symbol address series instructions.
Those two kinds of instruction have relationship be

[CSKY 6/n] Add support branch and symbol series instruction

This patch adds basic CSKY branch instructions and symbol address series instructions.
Those two kinds of instruction have relationship between each other, and it involves much work about Fixups.

For now, basic instructions are enabled except for disassembler support.
We would support to generate basic codegen asm firstly and delay disassembler work later.

Differential Revision: https://reviews.llvm.org/D95029

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[CSKY 5/n] Add support for all CSKY basic integer instructions except for branch series

This patch adds basic CSKY integer instructions except for branch series such as bsr, br.
It mainly includes b

[CSKY 5/n] Add support for all CSKY basic integer instructions except for branch series

This patch adds basic CSKY integer instructions except for branch series such as bsr, br.
It mainly includes basic ALU, load & store, compare and data move instructions.

Branch series instructions need handle complex symbol operand as following patch later.

Differential Revision: https://reviews.llvm.org/D94007

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[CSKY 4/n] Add basic CSKYAsmParser and CSKYInstPrinter

This basic parser will handle basic instructions with register or immediate operands.
With the addition of CSKYInstPrinter, we can now make use

[CSKY 4/n] Add basic CSKYAsmParser and CSKYInstPrinter

This basic parser will handle basic instructions with register or immediate operands.
With the addition of CSKYInstPrinter, we can now make use of lit tests.

Differential Revision: https://reviews.llvm.org/D93798

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