| /llvm-project-15.0.7/llvm/lib/Transforms/Scalar/ |
| H A D | ScalarizeMaskedMemIntrin.cpp | 197 if (VectorWidth != 1) { in scalarizeMaskedLoad()
213 VectorWidth, adjustForEndian(DL, VectorWidth, Idx))); in scalarizeMaskedLoad()
332 if (VectorWidth != 1) { in scalarizeMaskedStore()
347 VectorWidth, adjustForEndian(DL, VectorWidth, Idx))); in scalarizeMaskedStore()
453 if (VectorWidth != 1) { in scalarizeMaskedGather()
469 VectorWidth, adjustForEndian(DL, VectorWidth, Idx))); in scalarizeMaskedGather()
581 if (VectorWidth != 1) { in scalarizeMaskedScatter()
596 VectorWidth, adjustForEndian(DL, VectorWidth, Idx))); in scalarizeMaskedScatter()
686 if (VectorWidth != 1) { in scalarizeMaskedExpandLoad()
702 VectorWidth, adjustForEndian(DL, VectorWidth, Idx))); in scalarizeMaskedExpandLoad()
[all …]
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| /llvm-project-15.0.7/llvm/lib/Target/ARM/ |
| H A D | MVETailPredication.cpp | 214 int VectorWidth = in IsSafeActiveMask() local
216 if (VectorWidth != 2 && VectorWidth != 4 && VectorWidth != 8 && in IsSafeActiveMask()
217 VectorWidth != 16) in IsSafeActiveMask()
243 (ConstElemCount->getZExtValue() + VectorWidth - 1) / VectorWidth; in IsSafeActiveMask()
270 SE->getSCEV(ConstantInt::get(TripCount->getType(), VectorWidth - 1))); in IsSafeActiveMask()
281 dbgs() << "ARM TP: - VecWidth = " << VectorWidth << "\n"; in IsSafeActiveMask()
344 if (VectorWidth == StepValue) in IsSafeActiveMask()
348 << " doesn't match vector width " << VectorWidth << "\n"); in IsSafeActiveMask()
358 unsigned VectorWidth = in InsertVCTPIntrinsic() local
369 ConstantInt *Factor = ConstantInt::get(cast<IntegerType>(Ty), VectorWidth); in InsertVCTPIntrinsic()
[all …]
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| /llvm-project-15.0.7/polly/lib/Transform/ |
| H A D | ScheduleOptimizer.cpp | 288 int VectorWidth);
332 int VectorWidth);
365 int VectorWidth) { in isolateFullPartialTiles() argument
371 isl::set IsolateDomain = getPartialTilePrefixes(ScheduleRange, VectorWidth); in isolateFullPartialTiles()
395 isl::schedule_node Node, unsigned DimToVectorize, int VectorWidth) { in prevectSchedBand() argument
411 Sizes = Sizes.set_val(0, isl::val(Node.ctx(), VectorWidth)); in prevectSchedBand()
414 Node = isolateFullPartialTiles(Node, VectorWidth); in prevectSchedBand()
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| H A D | ScheduleTreeTransform.cpp | 546 static isl::set addExtentConstraints(isl::set Set, int VectorWidth) { in addExtentConstraints() argument
556 ExtConstr = ExtConstr.set_constant_si(VectorWidth - 1); in addExtentConstraints()
1114 int VectorWidth) { in getPartialTilePrefixes() argument
1119 auto ExtentPrefixes = addExtentConstraints(LoopPrefixes, VectorWidth); in getPartialTilePrefixes()
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| /llvm-project-15.0.7/polly/lib/CodeGen/ |
| H A D | BlockGenerators.cpp | 1043 unsigned VectorWidth = getVectorWidth(); in generateStrideOneLoad() local
1047 unsigned Offset = NegativeStride ? VectorWidth - 1 : 0; in generateStrideOneLoad()
1060 for (int i = VectorWidth - 1; i >= 0; i--) in generateStrideOneLoad()
1098 int VectorWidth = getVectorWidth(); in generateUnknownStrideLoad() local
1100 auto *FVTy = FixedVectorType::get(ElemTy, VectorWidth); in generateUnknownStrideLoad()
1104 for (int i = 0; i < VectorWidth; i++) { in generateUnknownStrideLoad()
1154 int VectorWidth = getVectorWidth(); in copyUnaryInst() local
1229 int VectorWidth = getVectorWidth(); in extractScalarValues() local
1240 for (int i = 0; i < VectorWidth; ++i) { in extractScalarValues()
1261 int VectorWidth = getVectorWidth(); in copyInstScalarized() local
[all …]
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| H A D | IslNodeBuilder.cpp | 426 int VectorWidth = in createMark() local
428 if (Vector && 1 < VectorWidth && VectorWidth <= 16) in createMark()
429 createForVector(Child, VectorWidth); in createMark()
460 int VectorWidth) { in createForVector() argument
479 std::vector<Value *> IVS(VectorWidth); in createForVector()
482 for (int i = 1; i < VectorWidth; i++) in createForVector()
796 int VectorWidth = in createFor() local
798 if (1 < VectorWidth && VectorWidth <= 16 && !hasPartialAccesses(For)) { in createFor()
799 createForVector(For, VectorWidth); in createFor()
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| /llvm-project-15.0.7/llvm/lib/Target/X86/ |
| H A D | X86InterleavedAccess.cpp | 614 int VectorWidth = VT.getSizeInBits(); in group2Shuffle() local
617 int Lane = (VectorWidth / 128 > 0) ? VectorWidth / 128 : 1; in group2Shuffle()
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| /llvm-project-15.0.7/polly/include/polly/CodeGen/ |
| H A D | IslNodeBuilder.h | 313 void createForVector(__isl_take isl_ast_node *For, int VectorWidth);
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| /llvm-project-15.0.7/polly/include/polly/ |
| H A D | ScheduleTreeTransform.h | 235 isl::set getPartialTilePrefixes(isl::set ScheduleRange, int VectorWidth);
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| /llvm-project-15.0.7/llvm/lib/CodeGen/GlobalISel/ |
| H A D | IRTranslator.cpp | 1495 unsigned VectorWidth = 0; in translateGetElementPtr() local
1501 VectorWidth = cast<FixedVectorType>(VT)->getNumElements(); in translateGetElementPtr()
1503 WantSplatVector = VectorWidth > 1; in translateGetElementPtr()
1511 .buildSplatVector(LLT::fixed_vector(VectorWidth, PtrTy), BaseReg) in translateGetElementPtr()
1513 PtrIRTy = FixedVectorType::get(PtrIRTy, VectorWidth); in translateGetElementPtr()
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| /llvm-project-15.0.7/llvm/lib/Target/WebAssembly/ |
| H A D | WebAssemblyISelLowering.cpp | 2627 const SDLoc &DL, unsigned VectorWidth) { in extractSubVector() argument
2630 unsigned Factor = VT.getSizeInBits() / VectorWidth; in extractSubVector()
2635 unsigned ElemsPerChunk = VectorWidth / ElVT.getSizeInBits(); in extractSubVector()
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| /llvm-project-15.0.7/clang/include/clang/Basic/ |
| H A D | Attr.td | 2798 let Args = [UnsignedArgument<"VectorWidth">];
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| /llvm-project-15.0.7/clang/lib/CodeGen/ |
| H A D | CGBuiltin.cpp | 5264 if (unsigned VectorWidth = getContext().BuiltinInfo.getRequiredVectorWidth(BuiltinID)) in EmitBuiltinExpr() local
5265 LargestVectorWidth = std::max(LargestVectorWidth, VectorWidth); in EmitBuiltinExpr()
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