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Searched refs:VSELECT (Results 1 – 25 of 28) sorted by relevance

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/llvm-project-15.0.7/llvm/test/CodeGen/X86/
H A Dvshift-6.ll15 ; VSELECT(r, B, count);
19 ; r = VSELECT(r, C, count);
21 ; VSELECT(r, r+r, count);
H A D2011-12-15-vec_shift.ll13 ; Make sure we're masking and pcmp'ing the VSELECT conditon vector.
H A Dvselect-avx.ll126 ; We shouldn't try to lower this directly using VSELECT because we don't have
/llvm-project-15.0.7/llvm/lib/Target/VE/
H A DVVPNodes.def122 ADD_VVP_OP(VVP_SELECT,VSELECT) REGISTER_PACKED(VVP_SELECT)
/llvm-project-15.0.7/llvm/lib/Target/Mips/
H A DMipsSEISelLowering.cpp103 {ISD::SHL, ISD::SRA, ISD::SRL, ISD::SETCC, ISD::VSELECT}); in MipsSETargetLowering()
345 setOperationAction(ISD::VSELECT, Ty, Legal); in addMSAIntType()
390 setOperationAction(ISD::VSELECT, Ty, Legal); in addMSAFloatType()
704 return DAG.getNode(ISD::VSELECT, SDLoc(N), Ty, Cond, IfSet, IfClr); in performORCombine()
1039 case ISD::VSELECT: in PerformDAGCombine()
1610 return DAG.getNode(ISD::VSELECT, DL, VecTy, in lowerINTRINSIC_WO_CHAIN()
1625 return DAG.getNode(ISD::VSELECT, DL, VecTy, in lowerINTRINSIC_WO_CHAIN()
1633 return DAG.getNode(ISD::VSELECT, DL, Op->getValueType(0), in lowerINTRINSIC_WO_CHAIN()
1640 return DAG.getNode(ISD::VSELECT, DL, Op->getValueType(0), in lowerINTRINSIC_WO_CHAIN()
1671 return DAG.getNode(ISD::VSELECT, DL, Op->getValueType(0), in lowerINTRINSIC_WO_CHAIN()
[all …]
/llvm-project-15.0.7/llvm/include/llvm/CodeGen/
H A DISDOpcodes.h722 VSELECT, enumerator
H A DBasicTTIImpl.h1115 ISD = ISD::VSELECT;
H A DSelectionDAG.h1114 auto Opcode = Cond.getValueType().isVector() ? ISD::VSELECT : ISD::SELECT;
/llvm-project-15.0.7/llvm/lib/Target/Hexagon/
H A DHexagonISelLoweringHVX.cpp140 setOperationAction(ISD::VSELECT, P, Custom); in initializeHVXLowering()
273 setOperationAction(ISD::VSELECT, T, Custom); in initializeHVXLowering()
389 setTargetDAGCombine({ISD::SPLAT_VECTOR, ISD::VSELECT}); in initializeHVXLowering()
1975 SDValue VSel = DAG.getNode(ISD::VSELECT, dl, ValTy, Mask, Load, Thru); in LowerHvxMaskedOp()
2432 case ISD::VSELECT: in LowerHvxOperation()
2595 case ISD::VSELECT: { in PerformHvxDAGCombine()
2601 return DAG.getNode(ISD::VSELECT, dl, ty(Op), C0, Ops[2], Ops[1]); in PerformHvxDAGCombine()
H A DHexagonISelLowering.cpp1746 setOperationAction(ISD::VSELECT, MVT::v4i8, Custom); in HexagonTargetLowering()
1747 setOperationAction(ISD::VSELECT, MVT::v2i16, Custom); in HexagonTargetLowering()
1812 setTargetDAGCombine(ISD::VSELECT); in HexagonTargetLowering()
3231 case ISD::VSELECT: return LowerVSELECT(Op, DAG); in LowerOperation()
3317 } else if (Opc == ISD::VSELECT) { in PerformDAGCombine()
3325 SDValue VSel = DCI.DAG.getNode(ISD::VSELECT, dl, ty(Op), C0, in PerformDAGCombine()
/llvm-project-15.0.7/llvm/lib/CodeGen/SelectionDAG/
H A DLegalizeVectorTypes.cpp63 case ISD::VSELECT: R = ScalarizeVecRes_VSELECT(N); break; in ScalarizeVectorResult()
662 case ISD::VSELECT: in ScalarizeVectorOperand()
949 case ISD::VSELECT: in SplitVectorResult()
2721 case ISD::VSELECT: in SplitVectorOperand()
2841 DAG.getNode(ISD::VSELECT, DL, LoOpVT, LoMask, LoOp0, LoOp1); in SplitVecOp_VSELECT()
2843 DAG.getNode(ISD::VSELECT, DL, HiOpVT, HiMask, HiOp0, HiOp1); in SplitVecOp_VSELECT()
3670 case ISD::VSELECT: in WidenVectorResult()
5134 if (N->getOpcode() != ISD::VSELECT) in WidenVSELECTMask()
5442 case ISD::VSELECT: Res = WidenVecOp_VSELECT(N); break; in WidenVectorOperand()
H A DLegalizeVectorOps.cpp350 case ISD::VSELECT: in LegalizeOp()
731 case ISD::VSELECT: in Expand()
H A DSelectionDAGDumper.cpp288 case ISD::VSELECT: return "vselect"; in getOperationName()
H A DTargetLowering.cpp1632 case ISD::VSELECT: in SimplifyDemandedBits()
3141 case ISD::VSELECT: { in SimplifyDemandedVectorElts()
6333 if (isOperationLegalOrCustom(ISD::VSELECT, SETCCVT)) { in prepareUREMEqFold()
6338 return DAG.getNode(ISD::VSELECT, DL, SETCCVT, TautologicalInvertedChannels, in prepareUREMEqFold()
6595 !isOperationLegalOrCustom(ISD::VSELECT, SETCCVT)) in prepareSREMEqFold()
6621 SDValue Blended = DAG.getNode(ISD::VSELECT, DL, SETCCVT, DivisorIsIntMin, in prepareSREMEqFold()
8853 if (VT.isVector() && !isOperationLegalOrCustom(ISD::VSELECT, VT)) in expandIntMINMAX()
8905 if (VT.isVector() && !isOperationLegalOrCustom(ISD::VSELECT, VT)) in expandAddSubSat()
H A DLegalizeIntegerTypes.cpp80 case ISD::VSELECT: in PromoteIntegerResult()
1645 case ISD::VSELECT: in PromoteIntegerOperand()
1939 if (N->getOpcode() == ISD::VSELECT) in PromoteIntOp_SELECT()
H A DDAGCombiner.cpp1737 case ISD::VSELECT: return visitVSELECT(N); in visit()
2190 if (!N1.hasOneUse() || N1.getOpcode() != ISD::VSELECT) in foldSelectWithIdentityConstant()
5085 case ISD::VSELECT: in isSaturatingMinMax()
10251 assert((N->getOpcode() == ISD::SELECT || N->getOpcode() == ISD::VSELECT) && in foldBoolSelectToLogic()
11286 if (!(N0->getOpcode() == ISD::SELECT || N0->getOpcode() == ISD::VSELECT) || in tryToFoldExtendSelectLoad()
11676 if (LegalOperations || !TLI.isOperationLegalOrCustom(ISD::VSELECT, VT)) in matchVSelectOpSizesWithSetCC()
11680 if (VSel.getOpcode() != ISD::VSELECT || !VSel.hasOneUse() || in matchVSelectOpSizesWithSetCC()
11703 return DAG.getNode(ISD::VSELECT, DL, VT, SetCC, CastA, CastB); in matchVSelectOpSizesWithSetCC()
24561 Test.getValueType().isVector() ? ISD::VSELECT : ISD::SELECT, DL, VT, in buildSqrtEstimateImpl()
H A DSelectionDAG.cpp3229 case ISD::VSELECT: in computeKnownBits()
4107 case ISD::VSELECT: in ComputeNumSignBits()
6447 case ISD::VSELECT: in getNode()
11133 case ISD::VSELECT: in UnrollVectorOp()
/llvm-project-15.0.7/llvm/lib/Target/ARM/
H A DARMISelLowering.cpp189 setOperationAction(ISD::VSELECT, VT, Expand); in addTypeForNEON()
398 setOperationAction(ISD::VSELECT, VT, Legal); in addMVEVectorTypes()
451 setOperationAction(ISD::VSELECT, VT, Expand); in addMVEVectorTypes()
1568 setTargetDAGCombine(ISD::VSELECT); in ARMTargetLowering()
13090 } else if (N->getOpcode() == ISD::VSELECT) { in PerformVQDMULHCombine()
16765 if (Op0.getOpcode() == ISD::VSELECT && Op1.getOpcode() != ISD::VSELECT) in PerformFAddVSelectCombine()
16768 if (Op1.getOpcode() != ISD::VSELECT) in PerformFAddVSelectCombine()
16899 if (ResVT != RetTy || N0->getOpcode() != ISD::VSELECT || in PerformVECREDUCE_ADDCombine()
16951 if (ResVT != RetTy || N0->getOpcode() != ISD::VSELECT || in PerformVECREDUCE_ADDCombine()
17079 if (Op->getOpcode() == ISD::VSELECT) in PerformVECREDUCE_ADDCombine()
[all …]
/llvm-project-15.0.7/llvm/lib/Target/AArch64/
H A DAArch64ISelLowering.cpp897 setTargetDAGCombine({ISD::SELECT, ISD::VSELECT}); in AArch64TargetLowering()
1493 setOperationAction(ISD::VSELECT, VT, Expand); in addTypeForNEON()
1710 setOperationAction(ISD::VSELECT, VT, Custom); in addTypeForFixedLengthSVE()
5595 case ISD::VSELECT: in LowerOperation()
8349 return DAG.getNode(ISD::VSELECT, DL, Ty, SplatPred, TVal, FVal); in LowerSELECT()
16713 return DAG.getNode(ISD::VSELECT, SDLoc(N), N->getValueType(0), in performIntrinsicCombine()
18316 if (FirstUse->getOpcode() != ISD::VSELECT) in tryToWidenSetCCOperands()
18659 return DAG.getNode(ISD::VSELECT, SDLoc(N), NTy, in trySwapVSelectOperands()
18731 return DAG.getNode(ISD::VSELECT, SDLoc(N), ResVT, SetCC, in performVSelectCombine()
19554 case ISD::VSELECT: in PerformDAGCombine()
[all …]
/llvm-project-15.0.7/llvm/lib/Target/X86/
H A DX86ISelLowering.cpp2333 ISD::VSELECT, in X86TargetLowering()
8489 case ISD::VSELECT: in getFauxShuffleMask()
26360 unsigned OpcodeSelect = ISD::VSELECT; in getVectorMaskingNode()
43633 if (Vec.getOpcode() == ISD::VSELECT && in scalarizeExtEltFP()
44173 if (N->getOpcode() != ISD::VSELECT) in combineVSelectWithAllOnesOrZeros()
44378 if ((N->getOpcode() != ISD::VSELECT && in combineVSelectToBLENDV()
44422 if ((UI->getOpcode() != ISD::VSELECT && in combineVSelectToBLENDV()
54112 case ISD::VSELECT: in combineConcatVectorOps()
54327 if (Sel.getOpcode() != ISD::VSELECT || in narrowExtractedVectorSelect()
54531 if (IdxVal == 0 && InOpcode == ISD::VSELECT && in combineEXTRACT_SUBVECTOR()
[all …]
H A DX86ISelDAGToDAG.cpp773 (N->getOpcode() == ISD::VSELECT || N->getOpcode() == X86ISD::SELECTS) && in isProfitableToFormMaskedOp()
1032 case ISD::VSELECT: { in PreprocessISelDAG()
/llvm-project-15.0.7/llvm/lib/Target/RISCV/
H A DRISCVISelLowering.cpp501 {ISD::SELECT_CC, ISD::VSELECT, ISD::VP_MERGE, ISD::VP_SELECT}, VT, in RISCVTargetLowering()
840 setOperationAction(ISD::VSELECT, VT, Custom); in RISCVTargetLowering()
909 setOperationAction({ISD::VSELECT, ISD::SELECT}, VT, Custom); in RISCVTargetLowering()
2379 Vec = DAG.getNode(ISD::VSELECT, DL, VT, in lowerBUILD_VECTOR()
2857 return DAG.getNode(ISD::VSELECT, DL, VT, SelectMask, V1, V2); in lowerVECTOR_SHUFFLE()
3589 case ISD::VSELECT: in LowerOperation()
3897 return DAG.getNode(ISD::VSELECT, DL, VT, CondSplat, TrueV, FalseV); in lowerSELECT()
4223 return DAG.getNode(ISD::VSELECT, DL, VecVT, Src, SplatTrueVal, SplatZero); in lowerVectorMaskExt()
/llvm-project-15.0.7/llvm/lib/Target/AMDGPU/
H A DAMDGPUISelLowering.cpp384 ISD::SELECT, ISD::VSELECT, ISD::SELECT_CC, in AMDGPUTargetLowering()
402 ISD::VSELECT, ISD::SELECT_CC, ISD::FCOPYSIGN, ISD::VECTOR_SHUFFLE, in AMDGPUTargetLowering()
/llvm-project-15.0.7/llvm/include/llvm/Target/
H A DTargetSelectionDAG.td596 def vselect : SDNode<"ISD::VSELECT" , SDTVSelect>;
/llvm-project-15.0.7/llvm/lib/Target/PowerPC/
H A DPPCISelLowering.cpp818 setOperationAction(ISD::VSELECT, VT, Legal); in PPCTargetLowering()
1380 setTargetDAGCombine({ISD::ABS, ISD::VSELECT}); in PPCTargetLowering()
15839 case ISD::VSELECT: in PerformDAGCombine()
17483 assert((N->getOpcode() == ISD::VSELECT) && "Need VSELECT node here"); in combineVSelect()

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