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Searched refs:VSCALE (Results 1 – 23 of 23) sorted by relevance

/llvm-project-15.0.7/llvm/test/Analysis/CostModel/AArch64/
H A Dsve-scatter.ll16 ; CHECK-VSCALE-2-LABEL: 'masked_scatters'
20 ; CHECK-VSCALE-2-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret void
22 ; CHECK-VSCALE-1-LABEL: 'masked_scatters'
26 ; CHECK-VSCALE-1-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret void
41 ; CHECK-VSCALE-2-LABEL: 'masked_scatters_tune_generic'
45 ; CHECK-VSCALE-2-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret void
47 ; CHECK-VSCALE-1-LABEL: 'masked_scatters_tune_generic'
51 ; CHECK-VSCALE-1-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret void
71 ; CHECK-VSCALE-2-LABEL: 'masked_scatters_no_vscale_range'
80 ; CHECK-VSCALE-2-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret void
[all …]
H A Dsve-gather.ll16 ; CHECK-VSCALE-2-LABEL: 'masked_gathers'
20 ; CHECK-VSCALE-2-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret void
22 ; CHECK-VSCALE-1-LABEL: 'masked_gathers'
26 ; CHECK-VSCALE-1-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret void
41 ; CHECK-VSCALE-2-LABEL: 'masked_gathers_tune_generic'
45 ; CHECK-VSCALE-2-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret void
47 ; CHECK-VSCALE-1-LABEL: 'masked_gathers_tune_generic'
51 ; CHECK-VSCALE-1-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret void
71 ; CHECK-VSCALE-2-LABEL: 'masked_gathers_no_vscale_range'
80 ; CHECK-VSCALE-2-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret void
[all …]
/llvm-project-15.0.7/llvm/test/Transforms/LoopVectorize/
H A Dscalable-loop-unpredicated-body-scalar-tail.ll6 ; CHECKUF1-DAG: %[[VSCALE:.*]] = call i64 @llvm.vscale.i64()
7 ; CHECKUF1-DAG: %[[VSCALEX4:.*]] = shl i64 %[[VSCALE]], 2
11 ; CHECKUF1-DAG: %[[VSCALE:.*]] = call i64 @llvm.vscale.i64()
12 ; CHECKUF1-DAG: %[[VSCALEX4:.*]] = shl i64 %[[VSCALE]], 2
25 ; CHECKUF1: %[[VSCALE:.*]] = call i64 @llvm.vscale.i64()
26 ; CHECKUF1: %[[VSCALEX4:.*]] = shl i64 %[[VSCALE]], 2
38 ; CHECKUF2-DAG: %[[VSCALEX8:.*]] = shl i64 %[[VSCALE]], 3
52 ; CHECKUF2: %[[VSCALE:.*]] = call i32 @llvm.vscale.i32()
53 ; CHECKUF2: %[[VSCALE2:.*]] = shl i32 %[[VSCALE]], 2
64 ; CHECKUF2: %[[VSCALE2:.*]] = shl i32 %[[VSCALE]], 2
[all …]
/llvm-project-15.0.7/llvm/test/CodeGen/Generic/
H A Dexpand-vp-load-store.ll99 ; CHECK-NEXT: [[VSCALE:%.*]] = call i32 @llvm.vscale.i32()
110 ; CHECK-NEXT: [[VSCALE:%.*]] = call i32 @llvm.vscale.i32()
111 ; CHECK-NEXT: [[VLMAX:%.*]] = mul nuw i32 [[VSCALE]], 1
125 ; CHECK-NEXT: [[VSCALE:%.*]] = call i32 @llvm.vscale.i32()
136 ; CHECK-NEXT: [[VSCALE:%.*]] = call i32 @llvm.vscale.i32()
137 ; CHECK-NEXT: [[VLMAX:%.*]] = mul nuw i32 [[VSCALE]], 1
151 ; CHECK-NEXT: [[VSCALE:%.*]] = call i32 @llvm.vscale.i32()
162 ; CHECK-NEXT: [[VSCALE:%.*]] = call i32 @llvm.vscale.i32()
163 ; CHECK-NEXT: [[VLMAX:%.*]] = mul nuw i32 [[VSCALE]], 1
177 ; CHECK-NEXT: [[VSCALE:%.*]] = call i32 @llvm.vscale.i32()
[all …]
H A Dexpand-vp-gather-scatter.ll62 ; CHECK-NEXT: [[VSCALE:%.*]] = call i32 @llvm.vscale.i32()
63 ; CHECK-NEXT: [[SCALABLE_SIZE:%.*]] = mul nuw i32 [[VSCALE]], 2
75 ; CHECK-NEXT: [[VSCALE:%.*]] = call i32 @llvm.vscale.i32()
76 ; CHECK-NEXT: [[SCALABLE_SIZE:%.*]] = mul nuw i32 [[VSCALE]], 1
88 ; CHECK-NEXT: [[VSCALE:%.*]] = call i32 @llvm.vscale.i32()
89 ; CHECK-NEXT: [[SCALABLE_SIZE:%.*]] = mul nuw i32 [[VSCALE]], 2
101 ; CHECK-NEXT: [[VSCALE:%.*]] = call i32 @llvm.vscale.i32()
102 ; CHECK-NEXT: [[SCALABLE_SIZE:%.*]] = mul nuw i32 [[VSCALE]], 1
/llvm-project-15.0.7/llvm/test/Transforms/LoopVectorize/AArch64/
H A Dsve-extract-last-veclane.ll11 ; CHECK: %[[VSCALE:.*]] = call i32 @llvm.vscale.i32()
12 ; CHECK-NEXT: %[[VSCALE2:.*]] = shl i32 %[[VSCALE]], 2
41 ; CHECK: %[[VSCALE:.*]] = call i32 @llvm.vscale.i32()
42 ; CHECK-NEXT: %[[VSCALE2:.*]] = shl i32 %[[VSCALE]], 2
H A Dsve-low-trip-count.ll13 ; CHECK: [[VSCALE:%.*]] = call i64 @llvm.vscale.i64()
14 ; CHECK-NEXT: [[VF:%.*]] = mul i64 [[VSCALE]], 2
/llvm-project-15.0.7/llvm/test/Transforms/LoopStrengthReduce/RISCV/
H A Dicmp-zero.ll191 ; CHECK-NEXT: [[VSCALE:%.*]] = call i64 @llvm.vscale.i64()
192 ; CHECK-NEXT: [[UREM:%.*]] = urem i64 [[N:%.*]], [[VSCALE]]
222 ; CHECK-NEXT: [[VSCALE:%.*]] = call i64 @llvm.vscale.i64()
223 ; CHECK-NEXT: [[MUL:%.*]] = mul nuw nsw i64 [[VSCALE]], 8
256 ; CHECK-NEXT: [[VSCALE:%.*]] = call i64 @llvm.vscale.i64()
257 ; CHECK-NEXT: [[MUL:%.*]] = mul nuw nsw i64 [[VSCALE]], 64
289 ; CHECK-NEXT: [[VSCALE:%.*]] = call i64 @llvm.vscale.i64()
290 ; CHECK-NEXT: [[SHL:%.*]] = shl i64 [[VSCALE]], 3
322 ; CHECK-NEXT: [[VSCALE:%.*]] = call i64 @llvm.vscale.i64()
323 ; CHECK-NEXT: [[SHL:%.*]] = shl i64 [[VSCALE]], 6
/llvm-project-15.0.7/llvm/test/CodeGen/AArch64/
H A Dsve-vscale-combine.ll76 ; At IR level, %shl = 2^4 * VSCALE.
77 ; At Assembly level, the output of RDVL is also 2^4 * VSCALE.
H A Dsve-lsr-scaled-index-addressing-mode.ll19 ; IR-NEXT: [[VSCALE:%.*]] = call i64 @llvm.vscale.i64()
20 ; IR-NEXT: [[SCALED_VF:%.*]] = shl i64 [[VSCALE]], 3
94 ; IR-NEXT: [[VSCALE:%.*]] = call i64 @llvm.vscale.i64()
95 ; IR-NEXT: [[SCALED_VF:%.*]] = shl i64 [[VSCALE]], 3
/llvm-project-15.0.7/llvm/test/CodeGen/RISCV/rvv/
H A Dcalling-conv.ll5 ; Check that we correctly scale the split part indirect offsets by VSCALE.
H A Dvadd-vp.ll1650 ; for ISD::VSCALE.
/llvm-project-15.0.7/llvm/include/llvm/CodeGen/
H A DISDOpcodes.h1249 VSCALE, enumerator
H A DSelectionDAG.h979 return getNode(ISD::VSCALE, DL, VT,
/llvm-project-15.0.7/llvm/lib/CodeGen/SelectionDAG/
H A DSelectionDAGDumper.cpp173 case ISD::VSCALE: return "vscale"; in getOperationName()
H A DSelectionDAG.cpp3901 if (Val.getOpcode() == ISD::VSCALE && in isKnownToBeAPowerOfTwo()
5303 if (OpOpcode == ISD::VSCALE && !NewNodesMustHaveLegalTypes) in getNode()
5376 case ISD::VSCALE: in getNode()
5970 if (N2C && (N1.getOpcode() == ISD::VSCALE) && Flags.hasNoSignedWrap()) { in getNode()
6032 if (N2C && (N1.getOpcode() == ISD::VSCALE) && Flags.hasNoSignedWrap()) { in getNode()
H A DDAGCombiner.cpp2664 if (N0.getOpcode() == ISD::VSCALE && N1.getOpcode() == ISD::VSCALE) { in visitADD()
2672 (N0.getOperand(1).getOpcode() == ISD::VSCALE) && in visitADD()
2673 (N1.getOpcode() == ISD::VSCALE)) { in visitADD()
3719 if (N1.getOpcode() == ISD::VSCALE) { in visitSUB()
4111 if (N0.getOpcode() == ISD::VSCALE) in visitMUL()
9115 if (N0.getOpcode() == ISD::VSCALE) in visitSHL()
H A DLegalizeIntegerTypes.cpp106 case ISD::VSCALE: Res = PromoteIntRes_VSCALE(N); break; in PromoteIntegerResult()
2558 case ISD::VSCALE: in ExpandIntegerResult()
H A DSelectionDAGBuilder.cpp3947 ISD::VSCALE, dl, VScaleTy, in visitGetElementPtr()
/llvm-project-15.0.7/llvm/lib/Target/RISCV/
H A DRISCVISelLowering.cpp423 setOperationAction(ISD::VSCALE, XLenVT, Custom); in RISCVTargetLowering()
3260 case ISD::VSCALE: { in LowerOperation()
5530 SlideupAmt = DAG.getNode(ISD::VSCALE, DL, XLenVT, SlideupAmt); in lowerINSERT_SUBVECTOR()
5537 VL = DAG.getNode(ISD::VSCALE, DL, XLenVT, VL); in lowerINSERT_SUBVECTOR()
5664 SlidedownAmt = DAG.getNode(ISD::VSCALE, DL, XLenVT, SlidedownAmt); in lowerEXTRACT_SUBVECTOR()
5770 SDValue VLMax = DAG.getNode(ISD::VSCALE, DL, XLenVT, in lowerVECTOR_REVERSE()
5802 SDValue VLMax = DAG.getNode(ISD::VSCALE, DL, XLenVT, in lowerVECTOR_SPLICE()
10999 Offset = DAG.getNode(ISD::VSCALE, DL, XLenVT, Offset); in LowerFormalArguments()
11289 Offset = DAG.getNode(ISD::VSCALE, DL, XLenVT, Offset); in LowerCall()
/llvm-project-15.0.7/llvm/include/llvm/Target/
H A DTargetSelectionDAG.td340 def vscale : SDNode<"ISD::VSCALE" , SDTIntUnaryOp, []>;
/llvm-project-15.0.7/llvm/lib/Target/AArch64/
H A DAArch64ISelDAGToDAG.cpp5202 if (VScale.getOpcode() != ISD::VSCALE) in SelectAddrModeIndexedSVE()
H A DAArch64ISelLowering.cpp1440 setOperationAction(ISD::VSCALE, MVT::i32, Custom); in AArch64TargetLowering()
5558 case ISD::VSCALE: in LowerOperation()
15092 if (VS.getOpcode() != ISD::VSCALE) in performLastTrueTestVectorCombine()