1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py 2; RUN: llc -mtriple=riscv32 -mattr=+m,+v < %s | FileCheck %s --check-prefixes=CHECK,RV32 3; RUN: llc -mtriple=riscv64 -mattr=+m,+v < %s | FileCheck %s --check-prefixes=CHECK,RV64 4 5; Check that we correctly scale the split part indirect offsets by VSCALE. 6define <vscale x 32 x i32> @callee_scalable_vector_split_indirect(<vscale x 32 x i32> %x, <vscale x 32 x i32> %y) { 7; CHECK-LABEL: callee_scalable_vector_split_indirect: 8; CHECK: # %bb.0: 9; CHECK-NEXT: csrr a1, vlenb 10; CHECK-NEXT: slli a1, a1, 3 11; CHECK-NEXT: add a1, a0, a1 12; CHECK-NEXT: vl8re32.v v24, (a0) 13; CHECK-NEXT: vl8re32.v v0, (a1) 14; CHECK-NEXT: vsetvli a0, zero, e32, m8, ta, mu 15; CHECK-NEXT: vadd.vv v8, v8, v24 16; CHECK-NEXT: vadd.vv v16, v16, v0 17; CHECK-NEXT: ret 18 %a = add <vscale x 32 x i32> %x, %y 19 ret <vscale x 32 x i32> %a 20} 21 22; Call the function above. Check that we set the arguments correctly. 23define <vscale x 32 x i32> @caller_scalable_vector_split_indirect(<vscale x 32 x i32> %x) { 24; RV32-LABEL: caller_scalable_vector_split_indirect: 25; RV32: # %bb.0: 26; RV32-NEXT: addi sp, sp, -144 27; RV32-NEXT: .cfi_def_cfa_offset 144 28; RV32-NEXT: sw ra, 140(sp) # 4-byte Folded Spill 29; RV32-NEXT: .cfi_offset ra, -4 30; RV32-NEXT: addi s0, sp, 144 31; RV32-NEXT: .cfi_def_cfa s0, 0 32; RV32-NEXT: csrr a0, vlenb 33; RV32-NEXT: slli a0, a0, 4 34; RV32-NEXT: sub sp, sp, a0 35; RV32-NEXT: andi sp, sp, -128 36; RV32-NEXT: addi a0, sp, 128 37; RV32-NEXT: vs8r.v v8, (a0) 38; RV32-NEXT: csrr a1, vlenb 39; RV32-NEXT: slli a1, a1, 3 40; RV32-NEXT: add a0, a0, a1 41; RV32-NEXT: vs8r.v v16, (a0) 42; RV32-NEXT: vsetvli a0, zero, e32, m8, ta, mu 43; RV32-NEXT: vmv.v.i v8, 0 44; RV32-NEXT: addi a0, sp, 128 45; RV32-NEXT: vmv.v.i v16, 0 46; RV32-NEXT: call callee_scalable_vector_split_indirect@plt 47; RV32-NEXT: addi sp, s0, -144 48; RV32-NEXT: lw ra, 140(sp) # 4-byte Folded Reload 49; RV32-NEXT: addi sp, sp, 144 50; RV32-NEXT: ret 51; 52; RV64-LABEL: caller_scalable_vector_split_indirect: 53; RV64: # %bb.0: 54; RV64-NEXT: addi sp, sp, -144 55; RV64-NEXT: .cfi_def_cfa_offset 144 56; RV64-NEXT: sd ra, 136(sp) # 8-byte Folded Spill 57; RV64-NEXT: .cfi_offset ra, -8 58; RV64-NEXT: addi s0, sp, 144 59; RV64-NEXT: .cfi_def_cfa s0, 0 60; RV64-NEXT: csrr a0, vlenb 61; RV64-NEXT: slli a0, a0, 4 62; RV64-NEXT: sub sp, sp, a0 63; RV64-NEXT: andi sp, sp, -128 64; RV64-NEXT: addi a0, sp, 128 65; RV64-NEXT: vs8r.v v8, (a0) 66; RV64-NEXT: csrr a1, vlenb 67; RV64-NEXT: slli a1, a1, 3 68; RV64-NEXT: add a0, a0, a1 69; RV64-NEXT: vs8r.v v16, (a0) 70; RV64-NEXT: vsetvli a0, zero, e32, m8, ta, mu 71; RV64-NEXT: vmv.v.i v8, 0 72; RV64-NEXT: addi a0, sp, 128 73; RV64-NEXT: vmv.v.i v16, 0 74; RV64-NEXT: call callee_scalable_vector_split_indirect@plt 75; RV64-NEXT: addi sp, s0, -144 76; RV64-NEXT: ld ra, 136(sp) # 8-byte Folded Reload 77; RV64-NEXT: addi sp, sp, 144 78; RV64-NEXT: ret 79 %c = alloca i64 80 %a = call <vscale x 32 x i32> @callee_scalable_vector_split_indirect(<vscale x 32 x i32> zeroinitializer, <vscale x 32 x i32> %x) 81 ret <vscale x 32 x i32> %a 82} 83