Lines Matching refs:VSCALE

6 ; CHECKUF1-DAG: %[[VSCALE:.*]] = call i64 @llvm.vscale.i64()
7 ; CHECKUF1-DAG: %[[VSCALEX4:.*]] = shl i64 %[[VSCALE]], 2
11 ; CHECKUF1-DAG:  %[[VSCALE:.*]] = call i64 @llvm.vscale.i64()
12 ; CHECKUF1-DAG:  %[[VSCALEX4:.*]] = shl i64 %[[VSCALE]], 2
25 ; CHECKUF1: %[[VSCALE:.*]] = call i64 @llvm.vscale.i64()
26 ; CHECKUF1: %[[VSCALEX4:.*]] = shl i64 %[[VSCALE]], 2
37 ; CHECKUF2-DAG: %[[VSCALE:.*]] = call i64 @llvm.vscale.i64()
38 ; CHECKUF2-DAG: %[[VSCALEX8:.*]] = shl i64 %[[VSCALE]], 3
42 ; CHECKUF2-DAG:  %[[VSCALE:.*]] = call i64 @llvm.vscale.i64()
43 ; CHECKUF2-DAG:  %[[VSCALEX8:.*]] = shl i64 %[[VSCALE]], 3
52 ; CHECKUF2: %[[VSCALE:.*]] = call i32 @llvm.vscale.i32()
53 ; CHECKUF2: %[[VSCALE2:.*]] = shl i32 %[[VSCALE]], 2
63 ; CHECKUF2: %[[VSCALE:.*]] = call i32 @llvm.vscale.i32()
64 ; CHECKUF2: %[[VSCALE2:.*]] = shl i32 %[[VSCALE]], 2
69 ; CHECKUF2: %[[VSCALE:.*]] = call i64 @llvm.vscale.i64()
70 ; CHECKUF2: %[[VSCALEX8:.*]] = shl i64 %[[VSCALE]], 3