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Searched refs:UINT_TO_FP (Results 1 – 25 of 40) sorted by relevance

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/llvm-project-15.0.7/llvm/lib/Target/X86/
H A DX86TargetTransformInfo.cpp1775 { ISD::UINT_TO_FP, MVT::v8f32, MVT::v8i64, 1 }, in getCastInstrCost()
1776 { ISD::UINT_TO_FP, MVT::v8f64, MVT::v8i64, 1 }, in getCastInstrCost()
1893 { ISD::UINT_TO_FP, MVT::v8f64, MVT::v8i1, 4 }, in getCastInstrCost()
1894 { ISD::UINT_TO_FP, MVT::v16f32, MVT::v16i1, 3 }, in getCastInstrCost()
1895 { ISD::UINT_TO_FP, MVT::v8f64, MVT::v16i8, 2 }, in getCastInstrCost()
1896 { ISD::UINT_TO_FP, MVT::v16f32, MVT::v16i8, 1 }, in getCastInstrCost()
1897 { ISD::UINT_TO_FP, MVT::v8f64, MVT::v8i16, 2 }, in getCastInstrCost()
1898 { ISD::UINT_TO_FP, MVT::v16f32, MVT::v16i16, 1 }, in getCastInstrCost()
1899 { ISD::UINT_TO_FP, MVT::v8f64, MVT::v8i32, 1 }, in getCastInstrCost()
1900 { ISD::UINT_TO_FP, MVT::v16f32, MVT::v16i32, 1 }, in getCastInstrCost()
[all …]
/llvm-project-15.0.7/llvm/lib/Target/ARM/
H A DARMTargetTransformInfo.cpp682 { ISD::UINT_TO_FP, MVT::v2f32, MVT::v2i8, 3 }, in getCastInstrCost()
768 { ISD::UINT_TO_FP, MVT::f32, MVT::i1, 2 }, in getCastInstrCost()
770 { ISD::UINT_TO_FP, MVT::f64, MVT::i1, 2 }, in getCastInstrCost()
772 { ISD::UINT_TO_FP, MVT::f32, MVT::i8, 2 }, in getCastInstrCost()
774 { ISD::UINT_TO_FP, MVT::f64, MVT::i8, 2 }, in getCastInstrCost()
776 { ISD::UINT_TO_FP, MVT::f32, MVT::i16, 2 }, in getCastInstrCost()
778 { ISD::UINT_TO_FP, MVT::f64, MVT::i16, 2 }, in getCastInstrCost()
780 { ISD::UINT_TO_FP, MVT::f32, MVT::i32, 2 }, in getCastInstrCost()
782 { ISD::UINT_TO_FP, MVT::f64, MVT::i32, 2 }, in getCastInstrCost()
784 { ISD::UINT_TO_FP, MVT::f32, MVT::i64, 10 }, in getCastInstrCost()
[all …]
H A DARMISelLowering.cpp174 setOperationAction(ISD::UINT_TO_FP, VT, Custom); in addTypeForNEON()
179 setOperationAction(ISD::UINT_TO_FP, VT, Expand); in addTypeForNEON()
305 setOperationAction(ISD::UINT_TO_FP, VT, Expand); in addMVEVectorTypes()
457 setOperationAction(ISD::UINT_TO_FP, VT, Expand); in addMVEVectorTypes()
468 setOperationAction(ISD::UINT_TO_FP, MVT::v2i1, Expand); in addMVEVectorTypes()
942 setOperationAction(ISD::UINT_TO_FP, MVT::v4i16, Custom); in ARMTargetLowering()
943 setOperationAction(ISD::UINT_TO_FP, MVT::v8i16, Custom); in ARMTargetLowering()
1058 setOperationAction(ISD::UINT_TO_FP, MVT::i32, Custom); in ARMTargetLowering()
5950 case ISD::UINT_TO_FP: in LowerVectorINT_TO_FP()
5952 Opc = ISD::UINT_TO_FP; in LowerVectorINT_TO_FP()
[all …]
/llvm-project-15.0.7/llvm/test/CodeGen/AMDGPU/
H A Ddagcombiner-bug-illegal-vec4-int-to-fp.ll7 ; ISD::UINT_TO_FP and ISD::SINT_TO_FP opcodes.
/llvm-project-15.0.7/llvm/lib/Target/AArch64/
H A DAArch64TargetTransformInfo.cpp1650 { ISD::UINT_TO_FP, MVT::v2f32, MVT::v2i32, 1 }, in getCastInstrCost()
1651 { ISD::UINT_TO_FP, MVT::v4f32, MVT::v4i32, 1 }, in getCastInstrCost()
1652 { ISD::UINT_TO_FP, MVT::v2f64, MVT::v2i64, 1 }, in getCastInstrCost()
1658 { ISD::UINT_TO_FP, MVT::v2f32, MVT::v2i8, 3 }, in getCastInstrCost()
1659 { ISD::UINT_TO_FP, MVT::v2f32, MVT::v2i16, 3 }, in getCastInstrCost()
1660 { ISD::UINT_TO_FP, MVT::v2f32, MVT::v2i64, 2 }, in getCastInstrCost()
1665 { ISD::UINT_TO_FP, MVT::v4f32, MVT::v4i8, 3 }, in getCastInstrCost()
1666 { ISD::UINT_TO_FP, MVT::v4f32, MVT::v4i16, 2 }, in getCastInstrCost()
1672 { ISD::UINT_TO_FP, MVT::v8f32, MVT::v8i16, 4 }, in getCastInstrCost()
1682 { ISD::UINT_TO_FP, MVT::v2f64, MVT::v2i8, 4 }, in getCastInstrCost()
[all …]
H A DAArch64ISelLowering.cpp476 setOperationAction(ISD::UINT_TO_FP, MVT::i32, Custom); in AArch64TargetLowering()
477 setOperationAction(ISD::UINT_TO_FP, MVT::i64, Custom); in AArch64TargetLowering()
478 setOperationAction(ISD::UINT_TO_FP, MVT::i128, Custom); in AArch64TargetLowering()
876 ISD::UINT_TO_FP}); in AArch64TargetLowering()
993 setOperationAction(ISD::UINT_TO_FP, MVT::v8i8, Custom); in AArch64TargetLowering()
1154 setOperationAction(ISD::UINT_TO_FP, VT, Custom); in AArch64TargetLowering()
1238 setOperationAction(ISD::UINT_TO_FP, VT, Custom); in AArch64TargetLowering()
1693 setOperationAction(ISD::UINT_TO_FP, VT, Custom); in addTypeForFixedLengthSVE()
5496 case ISD::UINT_TO_FP: in LowerOperation()
14537 (Opc != ISD::SINT_TO_FP && Opc != ISD::UINT_TO_FP)) in performFDivCombine()
[all …]
/llvm-project-15.0.7/llvm/include/llvm/IR/
H A DConstrainedOps.def59 DAG_INSTRUCTION(UIToFP, 1, 1, experimental_constrained_uitofp, UINT_TO_FP)
/llvm-project-15.0.7/llvm/include/llvm/CodeGen/
H A DISDOpcodes.h774 UINT_TO_FP, enumerator
/llvm-project-15.0.7/llvm/lib/Target/LoongArch/
H A DLoongArchISelLowering.cpp90 setOperationAction(ISD::UINT_TO_FP, GRLenVT, Custom); in LoongArchTargetLowering()
138 case ISD::UINT_TO_FP: in LowerOperation()
154 SDValue Res = DAG.getNode(ISD::UINT_TO_FP, DL, MVT::f64, Trunc); in lowerUINT_TO_FP()
/llvm-project-15.0.7/llvm/lib/CodeGen/SelectionDAG/
H A DLegalizeVectorOps.cpp429 case ISD::UINT_TO_FP: in LegalizeOp()
545 case ISD::UINT_TO_FP: in Promote()
617 unsigned Opc = (Node->getOpcode() == ISD::UINT_TO_FP || in PromoteINT_TO_FP()
757 case ISD::UINT_TO_FP: in Expand()
H A DSelectionDAGDumper.cpp354 case ISD::UINT_TO_FP: return "uint_to_fp"; in getOperationName()
H A DLegalizeFloatTypes.cpp138 case ISD::UINT_TO_FP: R = SoftenFloatRes_XINT_TO_FP(N); break; in SoftenFloatResult()
1274 case ISD::UINT_TO_FP: ExpandFloatRes_XINT_TO_FP(N, Lo, Hi); break; in ExpandFloatResult()
2299 case ISD::UINT_TO_FP: R = PromoteFloatRes_XINT_TO_FP(N); break; in PromoteFloatResult()
2662 case ISD::UINT_TO_FP: R = SoftPromoteHalfRes_XINT_TO_FP(N); break; in SoftPromoteHalfResult()
H A DLegalizeDAG.cpp1003 case ISD::UINT_TO_FP: in LegalizeOp()
2544 unsigned UIntOp = IsStrict ? ISD::STRICT_UINT_TO_FP : ISD::UINT_TO_FP; in PromoteLegalINT_TO_FP()
2956 case ISD::UINT_TO_FP: in ExpandNode()
4246 case ISD::UINT_TO_FP: { in ConvertNodeToLibcall()
4450 if (Node->getOpcode() == ISD::UINT_TO_FP || in PromoteNode()
4525 case ISD::UINT_TO_FP: in PromoteNode()
H A DLegalizeVectorTypes.cpp109 case ISD::UINT_TO_FP: in ScalarizeVectorResult()
647 case ISD::UINT_TO_FP: in ScalarizeVectorOperand()
1047 case ISD::UINT_TO_FP: in SplitVectorResult()
2727 case ISD::UINT_TO_FP: in SplitVectorOperand()
3821 case ISD::UINT_TO_FP: in WidenVectorResult()
5462 case ISD::UINT_TO_FP: in WidenVectorOperand()
/llvm-project-15.0.7/llvm/lib/Target/RISCV/
H A DRISCVTargetTransformInfo.cpp296 case ISD::UINT_TO_FP: in getCastInstrCost()
/llvm-project-15.0.7/llvm/lib/Target/AMDGPU/
H A DAMDGPUISelLowering.cpp360 {ISD::UINT_TO_FP, ISD::SINT_TO_FP, ISD::FP_TO_SINT, ISD::FP_TO_UINT}, in AMDGPUTargetLowering()
381 ISD::UINT_TO_FP, ISD::SDIV, ISD::UDIV, in AMDGPUTargetLowering()
1169 case ISD::UINT_TO_FP: return LowerUINT_TO_FP(Op, DAG); in LowerOperation()
1595 ISD::NodeType ToFp = Sign ? ISD::SINT_TO_FP : ISD::UINT_TO_FP; in LowerDIVREM24()
1733 SDValue Cvt_Lo = DAG.getNode(ISD::UINT_TO_FP, DL, MVT::f32, RHS_Lo); in LowerUDIVREM64()
1734 SDValue Cvt_Hi = DAG.getNode(ISD::UINT_TO_FP, DL, MVT::f32, RHS_Hi); in LowerUDIVREM64()
2388 (Signed && Subtarget->isGCN()) ? ISD::SINT_TO_FP : ISD::UINT_TO_FP; in LowerINT_TO_FP32()
2425 SDValue CvtHi = DAG.getNode(Signed ? ISD::SINT_TO_FP : ISD::UINT_TO_FP, in LowerINT_TO_FP64()
2428 SDValue CvtLo = DAG.getNode(ISD::UINT_TO_FP, SL, MVT::f64, Lo); in LowerINT_TO_FP64()
2450 return DAG.getNode(ISD::UINT_TO_FP, DL, DestVT, Ext); in LowerUINT_TO_FP()
H A DR600ISelLowering.cpp1709 if (Arg.getOpcode() == ISD::UINT_TO_FP && Arg.getValueType() == MVT::f64) { in PerformDAGCombine()
1710 return DAG.getNode(ISD::UINT_TO_FP, DL, N->getValueType(0), in PerformDAGCombine()
/llvm-project-15.0.7/llvm/lib/Target/Hexagon/
H A DHexagonISelLoweringHVX.cpp218 setOperationAction(ISD::UINT_TO_FP, T, Expand); in initializeHVXLowering()
223 setOperationAction(ISD::UINT_TO_FP, T, Custom); in initializeHVXLowering()
291 setOperationAction(ISD::UINT_TO_FP, T, Custom); in initializeHVXLowering()
2069 Opc == ISD::SINT_TO_FP || Opc == ISD::UINT_TO_FP); in LowerHvxConvertFpInt()
2404 case ISD::UINT_TO_FP: in LowerHvxOperation()
2474 case ISD::UINT_TO_FP: return LowerHvxConvertFpInt(Op, DAG); in LowerHvxOperation()
H A DHexagonISelLowering.cpp1767 setOperationAction(ISD::UINT_TO_FP, MVT::i1, Promote); in HexagonTargetLowering()
1768 setOperationAction(ISD::UINT_TO_FP, MVT::i8, Promote); in HexagonTargetLowering()
1769 setOperationAction(ISD::UINT_TO_FP, MVT::i16, Promote); in HexagonTargetLowering()
/llvm-project-15.0.7/llvm/lib/Target/PowerPC/
H A DPPCISelLowering.cpp257 AddPromotedToType(ISD::UINT_TO_FP, MVT::i1, in PPCTargetLowering()
277 setOperationAction(ISD::UINT_TO_FP, MVT::i1, Custom); in PPCTargetLowering()
521 setOperationAction(ISD::UINT_TO_FP, MVT::i32, Legal); in PPCTargetLowering()
535 setOperationAction(ISD::UINT_TO_FP, MVT::i32, Expand); in PPCTargetLowering()
1364 setTargetDAGCombine(ISD::UINT_TO_FP); in PPCTargetLowering()
8357 UI->getOpcode() != ISD::UINT_TO_FP && in directMoveIsProfitable()
11180 case ISD::UINT_TO_FP: in LowerOperation()
14410 FirstInput.getOpcode() != ISD::UINT_TO_FP) in DAGCombineBuildVector()
14413 N->getOperand(1).getOpcode() != ISD::UINT_TO_FP) in DAGCombineBuildVector()
14452 N->getOpcode() == ISD::UINT_TO_FP) && in combineFPToIntToFP()
[all …]
/llvm-project-15.0.7/llvm/lib/Target/WebAssembly/
H A DWebAssemblyISelLowering.cpp168 setTargetDAGCombine({ISD::SINT_TO_FP, ISD::UINT_TO_FP, ISD::FP_EXTEND, in WebAssemblyTargetLowering()
249 {ISD::SINT_TO_FP, ISD::UINT_TO_FP, ISD::FP_TO_SINT, ISD::FP_TO_UINT}) in WebAssemblyTargetLowering()
1986 case ISD::UINT_TO_FP: in LowerConvertLow()
/llvm-project-15.0.7/llvm/lib/Target/SystemZ/
H A DSystemZISelLowering.cpp270 setOperationAction(ISD::UINT_TO_FP, MVT::i32, Promote); in SystemZTargetLowering()
271 setOperationAction(ISD::UINT_TO_FP, MVT::i64, Expand); in SystemZTargetLowering()
416 setOperationAction(ISD::UINT_TO_FP, MVT::v2i64, Legal); in SystemZTargetLowering()
417 setOperationAction(ISD::UINT_TO_FP, MVT::v2f64, Legal); in SystemZTargetLowering()
436 setOperationAction(ISD::UINT_TO_FP, MVT::v4i32, Legal); in SystemZTargetLowering()
437 setOperationAction(ISD::UINT_TO_FP, MVT::v4f32, Legal); in SystemZTargetLowering()
657 ISD::UINT_TO_FP, in SystemZTargetLowering()
6780 (Opcode == ISD::UINT_TO_FP ? ISD::ZERO_EXTEND : ISD::SIGN_EXTEND); in combineINT_TO_FP()
7143 case ISD::UINT_TO_FP: return combineINT_TO_FP(N, DCI); in PerformDAGCombine()
/llvm-project-15.0.7/llvm/lib/Target/VE/
H A DVEISelLowering.cpp210 setOperationAction(ISD::UINT_TO_FP, MVT::i32, Promote); // use i64 in initSPUActions()
212 setOperationAction(ISD::UINT_TO_FP, MVT::i64, Expand); in initSPUActions()
2697 case ISD::UINT_TO_FP: in isI32Insn()
/llvm-project-15.0.7/llvm/lib/Target/Sparc/
H A DSparcISelLowering.cpp1615 setOperationAction(ISD::UINT_TO_FP, MVT::i32, Custom); in SparcTargetLowering()
1617 setOperationAction(ISD::UINT_TO_FP, MVT::i64, Custom); in SparcTargetLowering()
3145 case ISD::UINT_TO_FP: return LowerUINT_TO_FP(Op, DAG, *this, in LowerOperation()
3514 case ISD::UINT_TO_FP: in ReplaceNodeResults()
/llvm-project-15.0.7/llvm/test/CodeGen/AArch64/
H A Dsve-split-fcvt.ll346 ; UINT_TO_FP

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