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Searched refs:TypeWidenVector (Results 1 – 19 of 19) sorted by relevance

/llvm-project-15.0.7/llvm/lib/CodeGen/
H A DTargetLoweringBase.cpp1007 return LegalizeKind(TypeWidenVector, NVT); in getTypeConversion()
1070 return LegalizeKind(TypeWidenVector, LargerVector); in getTypeConversion()
1076 return LegalizeKind(TypeWidenVector, NVT); in getTypeConversion()
1430 case TypeWidenVector: in computeRegisterProperties()
1443 ValueTypeActions.setTypeAction(VT, TypeWidenVector); in computeRegisterProperties()
1455 ValueTypeActions.setTypeAction(VT, TypeWidenVector); in computeRegisterProperties()
1491 ValueTypeActions.setTypeAction(VT, TypeWidenVector); in computeRegisterProperties()
1545 (TA == TypeWidenVector || TA == TypePromoteInteger)) { in getVectorTypeBreakdown()
/llvm-project-15.0.7/llvm/lib/CodeGen/SelectionDAG/
H A DLegalizeVectorTypes.cpp1280 case TargetLowering::TypeWidenVector: in SplitVecRes_BITCAST()
2357 TypeAction == TargetLowering::TypeWidenVector)) in SplitVecRes_VECTOR_SHUFFLE()
4288 if (getTypeAction(InVT) == TargetLowering::TypeWidenVector) { in WidenVecRes_Convert()
4575 case TargetLowering::TypeWidenVector: in WidenVecRes_BITCAST()
4742 if (InOpTypeAction == TargetLowering::TypeWidenVector) in WidenVecRes_EXTRACT_SUBVECTOR()
4900 TargetLowering::TypeWidenVector && in WidenVecRes_VP_LOAD()
5537 TargetLowering::TypeWidenVector && in WidenVecOp_EXTEND()
5632 TargetLowering::TypeWidenVector && in WidenVecOp_Convert()
5785 TargetLowering::TypeWidenVector && in WidenVecOp_CONCAT_VECTORS()
5889 TargetLowering::TypeWidenVector && in WidenVecOp_VP_STORE()
[all …]
H A DLegalizeTypes.cpp286 case TargetLowering::TypeWidenVector: in run()
349 case TargetLowering::TypeWidenVector: in run()
H A DLegalizeTypesGeneric.cpp88 case TargetLowering::TypeWidenVector: { in ExpandRes_BITCAST()
H A DLegalizeTypes.h930 TargetLowering::TypeWidenVector && in GetWidenedMask()
H A DLegalizeIntegerTypes.cpp436 case TargetLowering::TypeWidenVector: in PromoteIntRes_BITCAST()
1386 case TargetLowering::TypeWidenVector: { in PromoteIntRes_TRUNCATE()
5206 if (getTypeAction(InVT) == TargetLowering::TypeWidenVector) { in PromoteIntRes_EXTRACT_SUBVECTOR()
H A DLegalizeFloatTypes.cpp2375 case TargetLowering::TypeWidenVector: { in PromoteFloatRes_EXTRACT_VECTOR_ELT()
H A DSelectionDAGBuilder.cpp673 TargetLowering::TypeWidenVector) { in getCopyToPartsVector()
/llvm-project-15.0.7/llvm/lib/Target/SystemZ/
H A DSystemZISelLowering.h415 return TypeWidenVector; in getPreferredVectorAction()
/llvm-project-15.0.7/llvm/lib/Target/Hexagon/
H A DHexagonSubtarget.cpp245 return Action == TargetLoweringBase::TypeWidenVector; in isTypeForHVX()
H A DHexagonISelLoweringHVX.cpp373 if (Action == TargetLoweringBase::TypeWidenVector) { in initializeHVXLowering()
422 return TargetLoweringBase::TypeWidenVector; in getPreferredHvxVectorAction()
425 return TargetLoweringBase::TypeWidenVector; in getPreferredHvxVectorAction()
2640 if (Action == TargetLoweringBase::TypeWidenVector) { in shouldWidenToHvx()
H A DHexagonISelLowering.cpp2165 return TargetLoweringBase::TypeWidenVector; in getPreferredVectorAction()
2170 return TargetLoweringBase::TypeWidenVector; in getPreferredVectorAction()
/llvm-project-15.0.7/llvm/unittests/CodeGen/
H A DAArch64SelectionDAGTest.cpp572 EXPECT_EQ(getTypeAction(FromVT), TargetLoweringBase::TypeWidenVector); in TEST_F()
/llvm-project-15.0.7/llvm/lib/Target/PowerPC/
H A DPPCISelLowering.h781 return TypeWidenVector; in getPreferredVectorAction()
/llvm-project-15.0.7/llvm/include/llvm/CodeGen/
H A DTargetLowering.h213 TypeWidenVector, // This vector should be widened into a larger vector. enumerator
466 return TypeWidenVector; in getPreferredVectorAction()
/llvm-project-15.0.7/llvm/lib/Target/WebAssembly/
H A DWebAssemblyISelLowering.cpp904 return TypeWidenVector; in getPreferredVectorAction()
/llvm-project-15.0.7/llvm/lib/Target/X86/
H A DX86ISelLowering.cpp2436 return TypeWidenVector; in getPreferredVectorAction()
25706 TargetLowering::TypeWidenVector && in LowerStore()
32427 assert(getTypeAction(*DAG.getContext(), VT) == TypeWidenVector && in ReplaceNodeResults()
32446 assert(getTypeAction(*DAG.getContext(), VT) == TypeWidenVector && in ReplaceNodeResults()
32488 assert(getTypeAction(*DAG.getContext(), VT) == TypeWidenVector && in ReplaceNodeResults()
32530 assert(getTypeAction(*DAG.getContext(), VT) == TypeWidenVector && in ReplaceNodeResults()
32555 if (getTypeAction(*DAG.getContext(), VT) != TypeWidenVector) in ReplaceNodeResults()
32776 assert(getTypeAction(*DAG.getContext(), VT) == TypeWidenVector && in ReplaceNodeResults()
32827 assert(getTypeAction(*DAG.getContext(), VT) == TypeWidenVector && in ReplaceNodeResults()
33365 assert(getTypeAction(*DAG.getContext(), VT) == TypeWidenVector && in ReplaceNodeResults()
[all …]
/llvm-project-15.0.7/llvm/lib/Target/AMDGPU/
H A DSIISelLowering.cpp1589 return VT.isPow2VectorType() ? TypeSplitVector : TypeWidenVector; in getPreferredVectorAction()
/llvm-project-15.0.7/llvm/lib/Target/AArch64/
H A DAArch64ISelLowering.cpp20385 return TypeWidenVector; in getPreferredVectorAction()