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Searched refs:Tmp0 (Results 1 – 14 of 14) sorted by relevance

/llvm-project-15.0.7/clang/test/CodeGenOpenCL/
H A Damdgpu-debug-info-pointer-address-space.cl49 private int *Tmp0;
59 private int *FuncVar3 = Tmp0;
81 private int *local FuncVar13; FuncVar13 = Tmp0;
92 private int *private FuncVar18 = Tmp0;
H A Damdgpu-debug-info-variable-expression.cl63 private int *Tmp0;
77 private int *FuncVar3 = Tmp0;
109 private int *local FuncVar13; FuncVar13 = Tmp0;
125 private int *private FuncVar18 = Tmp0;
/llvm-project-15.0.7/llvm/lib/Target/X86/
H A DX86ISelDAGToDAG.cpp3877 SDValue Tmp0, Tmp1, Tmp2, Tmp3, Tmp4; in matchBEXTRFromAndImm() local
3913 SDValue Tmp0, Tmp1, Tmp2, Tmp3, Tmp4; in emitPCMPISTR() local
3946 SDValue Tmp0, Tmp1, Tmp2, Tmp3, Tmp4; in emitPCMPESTR() local
4218 SDValue Tmp0, Tmp1, Tmp2, Tmp3, Tmp4; in matchVPTERNLOG() local
4604 SDValue Tmp0, Tmp1, Tmp2, Tmp3, Tmp4; in tryVPTESTM() local
5104 SDValue Tmp0, Tmp1, Tmp2, Tmp3, Tmp4; in Select() local
5157 SDValue Tmp0, Tmp1, Tmp2, Tmp3, Tmp4; in Select() local
5239 SDValue Tmp0, Tmp1, Tmp2, Tmp3, Tmp4; in Select() local
5373 SDValue Tmp0, Tmp1, Tmp2, Tmp3, Tmp4; in Select() local
5381 SDValue Tmp0, Tmp1, Tmp2, Tmp3, Tmp4, Chain; in Select() local
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H A DX86ISelLowering.cpp37107 unsigned Tmp0 = SrcBits, Tmp1 = SrcBits; in ComputeNumSignBitsForTargetNode() local
37112 unsigned Tmp = std::min(Tmp0, Tmp1); in ComputeNumSignBitsForTargetNode()
37162 unsigned Tmp0 = in ComputeNumSignBitsForTargetNode() local
37164 if (Tmp0 == 1) return 1; // Early out. in ComputeNumSignBitsForTargetNode()
37167 return std::min(Tmp0, Tmp1); in ComputeNumSignBitsForTargetNode()
37172 if (Tmp0 == 1) return 1; // Early out. in ComputeNumSignBitsForTargetNode()
37174 return std::min(Tmp0, Tmp1); in ComputeNumSignBitsForTargetNode()
37211 unsigned Tmp0 = VTBits; in ComputeNumSignBitsForTargetNode() local
37212 for (unsigned i = 0; i != NumOps && Tmp0 > 1; ++i) { in ComputeNumSignBitsForTargetNode()
37217 Tmp0 = std::min(Tmp0, Tmp1); in ComputeNumSignBitsForTargetNode()
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/llvm-project-15.0.7/llvm/test/Transforms/SLPVectorizer/X86/
H A Dsupernode.ll264 ; Tmp0 = A0 + 2.0
270 ; S[0] = Tmp0 + B0
306 %Tmp0 = fadd fast double %A0, 2.0
314 %Sum0 = fadd fast double %Tmp0, %B0
/llvm-project-15.0.7/llvm/lib/Target/AMDGPU/
H A DAMDGPUPromoteAlloca.cpp930 Value *Tmp0 = Builder.CreateMul(TCntY, TCntZ, "", true, true); in handleAlloca() local
931 Tmp0 = Builder.CreateMul(Tmp0, TIdX); in handleAlloca()
933 Value *TID = Builder.CreateAdd(Tmp0, Tmp1); in handleAlloca()
H A DAMDGPULegalizerInfo.cpp2171 auto Tmp0 = B.buildAnd(S64, Src, Not); in legalizeIntrinsicTrunc() local
2177 auto Tmp1 = B.buildSelect(S64, ExpLt0, SignBit64, Tmp0); in legalizeIntrinsicTrunc()
3820 auto Tmp0 = B.buildFMA(ResTy, NegY, R, One); in legalizeFastUnsafeFDIV64() local
3821 R = B.buildFMA(ResTy, Tmp0, R, R); in legalizeFastUnsafeFDIV64()
H A DAMDGPUISelLowering.cpp2099 SDValue Tmp0 = DAG.getNode(ISD::AND, SL, MVT::i64, BcInt, Not); in LowerFTRUNC() local
2109 SDValue Tmp1 = DAG.getNode(ISD::SELECT, SL, MVT::i64, ExpLt0, SignBit64, Tmp0); in LowerFTRUNC()
H A DSIISelLowering.cpp8865 SDValue Tmp0 = DAG.getNode(ISD::FMA, SL, VT, NegY, R, One); in lowerFastUnsafeFDIV64() local
8867 R = DAG.getNode(ISD::FMA, SL, VT, Tmp0, R, R); in lowerFastUnsafeFDIV64()
/llvm-project-15.0.7/llvm/lib/Transforms/Utils/
H A DIntegerDivision.cpp253 Value *Tmp0 = Builder.CreateCall(CTLZ, {Divisor, True}); in generateUnsignedDivisionCode() local
255 Value *SR = Builder.CreateSub(Tmp0, Tmp1); in generateUnsignedDivisionCode()
/llvm-project-15.0.7/llvm/lib/Target/Hexagon/
H A DHexagonVectorCombine.cpp451 Value *Tmp0 = in createAdjustedPointer() local
453 return Builder.CreatePointerCast(Tmp0, ValTy->getPointerTo()); in createAdjustedPointer()
458 Value *Tmp0 = Builder.CreatePointerCast(Ptr, CharPtrTy); in createAdjustedPointer() local
459 Value *Tmp1 = Builder.CreateGEP(Type::getInt8Ty(HVC.F.getContext()), Tmp0, in createAdjustedPointer()
/llvm-project-15.0.7/llvm/lib/Target/WebAssembly/
H A DWebAssemblyISelLowering.cpp473 unsigned Tmp0, Tmp1, CmpReg, EqzReg, FalseReg, TrueReg; in LowerFPToInt() local
474 Tmp0 = MRI.createVirtualRegister(MRI.getRegClass(InReg)); in LowerFPToInt()
485 Tmp0 = InReg; in LowerFPToInt()
487 BuildMI(BB, DL, TII.get(Abs), Tmp0).addReg(InReg); in LowerFPToInt()
491 BuildMI(BB, DL, TII.get(LT), CmpReg).addReg(Tmp0).addReg(Tmp1); in LowerFPToInt()
501 BuildMI(BB, DL, TII.get(GE), SecondCmpReg).addReg(Tmp0).addReg(Tmp1); in LowerFPToInt()
/llvm-project-15.0.7/llvm/lib/Target/ARM/
H A DARMISelLowering.cpp5982 SDValue Tmp0 = Op.getOperand(0); in LowerFCOPYSIGN() local
5987 bool InGPR = Tmp0.getOpcode() == ISD::BITCAST || in LowerFCOPYSIGN()
5988 Tmp0.getOpcode() == ARMISD::VMOVDRR; in LowerFCOPYSIGN()
6002 Tmp0 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2f32, Tmp0); in LowerFCOPYSIGN()
6013 Tmp0 = DAG.getNode(ISD::BITCAST, dl, OpVT, Tmp0); in LowerFCOPYSIGN()
6047 Tmp0 = DAG.getNode(ISD::AND, dl, MVT::i32, in LowerFCOPYSIGN()
6050 DAG.getNode(ISD::OR, dl, MVT::i32, Tmp0, Tmp1)); in LowerFCOPYSIGN()
6054 Tmp0 = DAG.getNode(ARMISD::VMOVRRD, dl, DAG.getVTList(MVT::i32, MVT::i32), in LowerFCOPYSIGN()
6055 Tmp0); in LowerFCOPYSIGN()
6056 SDValue Lo = Tmp0.getValue(0); in LowerFCOPYSIGN()
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/llvm-project-15.0.7/llvm/lib/CodeGen/SelectionDAG/
H A DSelectionDAGBuilder.cpp8189 SDValue Tmp0 = getValue(I.getArgOperand(0)); in visitBinaryFloatCall() local
8191 EVT VT = Tmp0.getValueType(); in visitBinaryFloatCall()
8192 setValue(&I, DAG.getNode(Opcode, getCurSDLoc(), VT, Tmp0, Tmp1, Flags)); in visitBinaryFloatCall()