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Searched refs:TargetConstant (Results 1 – 25 of 33) sorted by relevance

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/llvm-project-15.0.7/llvm/test/tools/UpdateTestChecks/update_llc_test_checks/Inputs/
H A Dlanai_isel.ll.expected8 …oad (s32) from %fixed-stack.0)> TargetFrameIndex:i32<-2>, TargetConstant:i32<0>, TargetConstant:i3…
10 ; CHECK-NEXT: t29: i32 = OR_I_LO t7, TargetConstant:i32<4>
11 …renceable load (s32) from %ir.loc + 4, basealign 8)> t29, TargetConstant:i32<0>, TargetConstant:i3…
12 ; CHECK-NEXT: t24: i32 = ADD_R t5, t22, TargetConstant:i32<0>
13 … from %fixed-stack.1, align 8)> TargetFrameIndex:i32<-1>, TargetConstant:i32<0>, TargetConstant:i3…
17 ; CHECK-NEXT: t31: i32 = SCC TargetConstant:i32<4>, t30:1
55 ; CHECK-NEXT: t21: i32 = OR_I_LO t1, TargetConstant:i32<2>
56 … = LDHz_RI<Mem:(load (s16) from %fixed-stack.0 + 2)> t21, TargetConstant:i32<0>, TargetConstant:i3…
61 ; CHECK-NEXT: t28: i32 = TargetConstant<65535>
79 …h = LDBz_RI<Mem:(load (s8) from %fixed-stack.0 + 3)> t21, TargetConstant:i32<0>, TargetConstant:i3…
[all …]
H A Dx86_isel.ll.expected12 ; PIC-NEXT: t11: ch = RET TargetConstant:i32<0>, Register:i64 $rax, t10, t10:1
21 ; WIN-NEXT: t11: ch = RET TargetConstant:i32<0>, Register:i64 $rax, t10, t10:1
35 ; PIC-NEXT: t8: i64 = SUBREG_TO_REG TargetConstant:i64<0>, t7, TargetConstant:i32<6>
37 ; PIC-NEXT: t12: ch = RET TargetConstant:i32<0>, Register:i64 $rax, t11, t11:1
45 ; WIN-NEXT: t8: i64 = SUBREG_TO_REG TargetConstant:i64<0>, t7, TargetConstant:i32<6>
61 ; PIC-NEXT: t3: i16 = EXTRACT_SUBREG t2, TargetConstant:i32<4>
64 ; PIC-NEXT: t9: i64 = SUBREG_TO_REG TargetConstant:i64<0>, t15, TargetConstant:i32<6>
75 ; WIN-NEXT: t8: i64 = SUBREG_TO_REG TargetConstant:i64<0>, t14, TargetConstant:i32<6>
91 ; PIC-NEXT: t3: i8 = EXTRACT_SUBREG t2, TargetConstant:i32<1>
94 ; PIC-NEXT: t9: i64 = SUBREG_TO_REG TargetConstant:i64<0>, t15, TargetConstant:i32<6>
[all …]
H A Damdgpu_isel.ll.expected9 ; CHECK-NEXT: t17: i32 = V_MOV_B32_e32 TargetConstant:i32<0>
22 ; CHECK-NEXT: t5: i32 = V_MOV_B32_e32 TargetConstant:i32<0>
38 ; CHECK-NEXT: t5: i32 = V_MOV_B32_e32 TargetConstant:i32<0>
54 ; CHECK-NEXT: t5: i32 = V_MOV_B32_e32 TargetConstant:i32<0>
/llvm-project-15.0.7/llvm/test/CodeGen/Mips/cstmaterialization/
H A Disel-materialization.ll21 ; MIPS-DAG: t{{[0-9]+}}: i32 = ADDiu Register:i32 $zero, TargetConstant:i32<1>
22 ; MIPS-DAG: t{{[0-9]+}}: i32 = ADDiu Register:i32 $zero, TargetConstant:i32<2048>
23 ; MIPS-DAG: t{{[0-9]+}}: i32 = LUi TargetConstant:i32<128>
26 ; MIPS: t[[A:[0-9]+]]: i32 = LUi TargetConstant:i32<2304>
27 ; MIPS: t{{[0-9]+}}: i32 = ORi t[[A]], TargetConstant:i32<2>
30 ; MM-DAG: t{{[0-9]+}}: i32 = LI16_MM TargetConstant:i32<1>
31 ; MM-DAG: t{{[0-9]+}}: i32 = ADDiu_MM Register:i32 $zero, TargetConstant:i32<2048>
32 ; MM-DAG: t{{[0-9]+}}: i32 = LUi_MM TargetConstant:i32<128>
35 ; MM: t[[A:[0-9]+]]: i32 = LUi_MM TargetConstant:i32<2304>
36 ; MM: t{{[0-9]+}}: i32 = ORi_MM t[[A]], TargetConstant:i32<2>
/llvm-project-15.0.7/llvm/test/CodeGen/Mips/cconv/
H A Dbyval.ll32 ; O32-SDAG: t{{.*}}: ch,glue = callseq_start t{{.*}}, TargetConstant:i32<{{.*}}>
37 ; O32-SDAG: t{{.*}}: ch,glue = callseq_end t{{.*}}, TargetConstant:i32<{{.*}}>
40 ; N32-SDAG: t{{.*}}: ch,glue = callseq_start t{{.*}}, TargetConstant:i32<{{.*}}>
45 ; N32-SDAG: t{{.*}}: ch,glue = callseq_end t{{.*}}, TargetConstant:i32<{{.*}}>
48 ; N64-SDAG: t{{.*}}: ch,glue = callseq_start t{{.*}}, TargetConstant:i64<{{.*}}>
53 ; N64-SDAG: t{{.*}}: ch,glue = callseq_end t{{.*}}, TargetConstant:i64<{{.*}}>
164 ; O32-SDAG: t{{.*}}: ch,glue = callseq_end t{{.*}}, TargetConstant:i32<{{.*}}>
170 ; O32-SDAG: t{{.*}}: ch,glue = callseq_end t{{.*}}, TargetConstant:i32<{{.*}}>
357 ; O32-SDAG: t{{.*}}: ch,glue = callseq_end t{{.*}}, TargetConstant:i32<16>
362 ; N32-SDAG: t{{.*}}: ch,glue = callseq_end t{{.*}}, TargetConstant:i32<0>
[all …]
/llvm-project-15.0.7/llvm/test/CodeGen/AArch64/
H A Dsve-fixed-length-frame-offests.ll14 ; CHECK-NEXT: t12: nxv2i1 = PTRUE_D TargetConstant:i32<31>
16 …18: nxv2i64,ch = LD1D_IMM<Mem:(volatile load (s512) from %ir.a)> t12, t2, TargetConstant:i64<0>, t0
17 ; CHECK-NEXT: t8: i64 = ADDXri TargetFrameIndex:i64<1>, TargetConstant:i32<0>, TargetConstant:i3…
18 …volatile store (s512) into %ir.r0)> t18, t12, TargetFrameIndex:i64<0>, TargetConstant:i64<0>, t18:1
19 …16: ch = ST1D_IMM<Mem:(volatile store (s512) into %ir.r1)> t18, t12, t8, TargetConstant:i64<0>, t17
H A Darm64-patchpoint.ll47 ; Test patchpoints reusing the same TargetConstant.
/llvm-project-15.0.7/llvm/test/CodeGen/X86/
H A Dcallbr-asm-bb-exports.ll20 …TargetConstant:i64<0>, TargetConstant:i32<2359305>, Register:i32 %5, TargetConstant:i64<13>, Targe…
H A Dfmf-propagation.ll53 ; CHECK: v16f32 = llvm.x86.avx512.vfmadd.ps.512 ninf nsz TargetConstant:i64<{{.*}}>
54 ; CHECK: v16f32 = llvm.x86.avx512.vfmadd.ps.512 nsz TargetConstant:i64<{{.*}}>
H A Dselectiondag-debug-loc.ll25 ; CHECK: X86ISD::RET_FLAG {{.*}}, TargetConstant:i32<0>, Register:i32 $eax, {{.*}}, <stdin>:2:3
H A Dvshli-simplify-demanded-bits.ll5 ; TargetConstant for the RHS operand.
H A Dpatchpoint.ll58 ; Test patchpoints reusing the same TargetConstant.
/llvm-project-15.0.7/llvm/test/CodeGen/VE/Scalar/
H A Dinlineasm-vldvst-reg.ll8 …:ch<null>, TargetConstant:i64<1>, TargetConstant:i32<589834>, Register:v512i32 %4, TargetConstant:…
/llvm-project-15.0.7/llvm/test/CodeGen/Mips/
H A Dframeindex.ll9 ; MIPS32: t{{[0-9]+}}: i{{[0-9]+}} = LEA_ADDiu TargetFrameIndex:i32<0>, TargetConstant:i32<0>
10 ; MM: t{{[0-9]+}}: i{{[0-9]+}} = LEA_ADDiu_MM TargetFrameIndex:i32<0>, TargetConstant:i32<0>
11 ; MIPS64: t{{[0-9]+}}: i{{[0-9]+}} = LEA_ADDiu64 TargetFrameIndex:i64<0>, TargetConstant:i64<0>
/llvm-project-15.0.7/llvm/test/CodeGen/PowerPC/
H A Dfmf-propagation.ll581 ; FMFDEBUG: ch,glue = callseq_end t15, TargetConstant:i64<32>, TargetConstant:i64<0>, t15:1
587 ; GLOBALDEBUG: ch,glue = callseq_end t15, TargetConstant:i64<32>, TargetConstant:i64<0>, t1…
H A Dppc64-patchpoint.ll70 ; Test patchpoints reusing the same TargetConstant.
/llvm-project-15.0.7/llvm/include/llvm/CodeGen/
H A DISDOpcodes.h158 TargetConstant, enumerator
H A DSelectionDAGNodes.h1575 : SDNode(isTarget ? ISD::TargetConstant : ISD::Constant, 0, DebugLoc(),
1606 N->getOpcode() == ISD::TargetConstant;
/llvm-project-15.0.7/llvm/test/CodeGen/SystemZ/
H A Dpatchpoint.ll57 ; Test patchpoints reusing the same TargetConstant.
/llvm-project-15.0.7/llvm/lib/Target/Mips/
H A DMipsSEISelDAGToDAG.cpp864 assert(Intrinsic.getOpcode() == ISD::TargetConstant && in trySelect()
936 assert(Intrinsic.getOpcode() == ISD::TargetConstant && in trySelect()
/llvm-project-15.0.7/llvm/lib/CodeGen/SelectionDAG/
H A DSelectionDAGDumper.cpp156 case ISD::TargetConstant: in getOperationName()
H A DLegalizeTypes.h81 return N->getOpcode() == ISD::TargetConstant || in IgnoreNodeResults()
H A DSelectionDAGISel.cpp2805 case ISD::TargetConstant: in SelectCodeCommon()
/llvm-project-15.0.7/llvm/include/llvm/Target/
H A DTargetSelectionDAG.td334 def timm : SDNode<"ISD::TargetConstant",SDTIntLeaf, [], "ConstantSDNode">;
920 // Convenience wrapper for ImmLeaf to use timm/TargetConstant instead
/llvm-project-15.0.7/llvm/lib/Target/PowerPC/
H A DPPCISelDAGToDAG.cpp233 if (N.getOpcode() == ISD::TargetConstant || in SelectAddrImmOffs()
4979 N->getOperand(1).getOpcode() == ISD::TargetConstant) in Select()
5281 if (Offset.getOpcode() == ISD::TargetConstant || in Select()

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