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Searched refs:TRC (Results 1 – 25 of 32) sorted by relevance

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/llvm-project-15.0.7/llvm/lib/Target/ARM/
H A DA15SDOptimizer.cpp74 unsigned Lane, const TargetRegisterClass *TRC);
97 bool usesRegClass(MachineOperand &MO, const TargetRegisterClass *TRC);
133 const TargetRegisterClass *TRC) { in usesRegClass() argument
139 return MRI->getRegClass(Reg)->hasSuperClassEq(TRC); in usesRegClass()
141 return TRC->contains(Reg); in usesRegClass()
269 const TargetRegisterClass *TRC = in optimizeSDPattern() local
271 if (TRC->hasSuperClassEq(MRI->getRegClass(FullReg))) { in optimizeSDPattern()
432 const TargetRegisterClass *TRC) { in createExtractSubreg() argument
433 Register Out = MRI->createVirtualRegister(TRC); in createExtractSubreg()
H A DARMLoadStoreOptimizer.cpp2434 const TargetRegisterClass *TRC = TII->getRegClass(MCID, 0, TRI, *MF); in RescheduleOps() local
2435 MRI->constrainRegClass(FirstReg, TRC); in RescheduleOps()
2436 MRI->constrainRegClass(SecondReg, TRC); in RescheduleOps()
2736 const TargetRegisterClass *TRC = TII->getRegClass(MCID, BaseOp, TRI, *MF); in AdjustBaseAndOffset() local
2737 MRI.constrainRegClass(NewBaseReg, TRC); in AdjustBaseAndOffset()
2793 const TargetRegisterClass *TRC = TII->getRegClass(MCID, 0, TRI, *MF); in createPostIncLoadStore() local
2794 MRI.constrainRegClass(NewReg, TRC); in createPostIncLoadStore()
2796 TRC = TII->getRegClass(MCID, 2, TRI, *MF); in createPostIncLoadStore()
2797 MRI.constrainRegClass(MI->getOperand(1).getReg(), TRC); in createPostIncLoadStore()
H A DARMISelLowering.cpp10815 VReg2 = MRI->createVirtualRegister(TRC); in EmitSjLjDispatchBlock()
10920 NewVReg6 = MRI->createVirtualRegister(TRC); in EmitSjLjDispatchBlock()
10952 VReg2 = MRI->createVirtualRegister(TRC); in EmitSjLjDispatchBlock()
11242 const TargetRegisterClass *TRC = nullptr; in EmitStructByval() local
11345 Register varEnd = MRI.createVirtualRegister(TRC); in EmitStructByval()
11349 Vtmp = MRI.createVirtualRegister(TRC); in EmitStructByval()
11393 Register varLoop = MRI.createVirtualRegister(TRC); in EmitStructByval()
11394 Register varPhi = MRI.createVirtualRegister(TRC); in EmitStructByval()
11395 Register srcLoop = MRI.createVirtualRegister(TRC); in EmitStructByval()
11396 Register srcPhi = MRI.createVirtualRegister(TRC); in EmitStructByval()
[all …]
/llvm-project-15.0.7/llvm/lib/Target/M68k/
H A DM68kRegisterInfo.cpp107 const TargetRegisterClass &TRC) const { in getRegisterOrder()
108 for (unsigned i = 0; i < TRC.getNumRegs(); ++i) { in getRegisterOrder()
109 if (regsOverlap(Reg, TRC.getRegister(i))) { in getRegisterOrder()
H A DM68kRegisterInfo.h77 int getRegisterOrder(unsigned Reg, const TargetRegisterClass &TRC) const;
/llvm-project-15.0.7/llvm/lib/CodeGen/SelectionDAG/
H A DInstrEmitter.cpp500 const TargetRegisterClass *TRC = in EmitSubregNode() local
519 TRC == MRI->getRegClass(SrcReg)) { in EmitSubregNode()
525 VRBase = MRI->createVirtualRegister(TRC); in EmitSubregNode()
539 VRBase = MRI->createVirtualRegister(TRC); in EmitSubregNode()
656 const TargetRegisterClass *TRC = MRI->getRegClass(SubReg); in EmitRegSequence() local
658 TRI->getMatchingSuperRegClass(RC, TRC, SubIdx); in EmitRegSequence()
/llvm-project-15.0.7/llvm/lib/CodeGen/
H A DMachineRegisterInfo.cpp492 const TargetRegisterClass &TRC = *getRegClass(Reg); in getMaxLaneMaskForVReg() local
493 return TRC.getLaneMask(); in getMaxLaneMaskForVReg()
H A DLiveDebugVariables.cpp1538 const TargetRegisterClass *TRC = MRI.getRegClass(VirtReg); in rewriteLocations() local
1539 bool Success = TII.getStackSlotRange(TRC, Loc.getSubReg(), SpillSize, in rewriteLocations()
1850 const TargetRegisterClass *TRC = MRI.getRegClass(Reg); in emitDebugValues() local
1853 unsigned regSizeInBits = TRI->getRegSizeInBits(*TRC); in emitDebugValues()
1861 TII->getStackSlotRange(TRC, SubReg, SpillSize, SpillOffset, *MF); in emitDebugValues()
H A DRegAllocPBQP.cpp617 const TargetRegisterClass *TRC = MRI.getRegClass(VReg); in initializeGraph() local
625 ArrayRef<MCPhysReg> RawPRegOrder = TRC->getRawAllocationOrder(MF); in initializeGraph()
/llvm-project-15.0.7/llvm/lib/Target/WebAssembly/
H A DWebAssemblyAsmPrinter.cpp61 const TargetRegisterClass *TRC = MRI->getRegClass(RegNo); in getRegType() local
64 if (TRI->isTypeLegalForClass(*TRC, T)) in getRegType()
H A DWebAssemblyISelLowering.cpp540 const TargetRegisterClass *TRC = MRI.getRegClass(Reg); in LowerCallResults() local
541 IsFuncrefCall = (TRC == &WebAssembly::FUNCREFRegClass); in LowerCallResults()
/llvm-project-15.0.7/clang/include/clang/AST/
H A DASTNodeTraverser.h432 if (const Expr *TRC = D->getTrailingRequiresClause()) in VisitFunctionDecl() local
433 Visit(TRC); in VisitFunctionDecl()
H A DDecl.h2500 if (auto *TRC = getTrailingRequiresClause()) in getAssociatedConstraints() local
2501 AC.push_back(TRC); in getAssociatedConstraints()
/llvm-project-15.0.7/llvm/lib/Target/X86/
H A DX86AvoidStoreForwardingBlocks.cpp557 const auto *TRC = TII->getRegClass(TII->get(LoadInst->getOpcode()), 0, TRI, in getRegSizeInBytes() local
559 return TRI->getRegSizeInBits(*TRC) / 8; in getRegSizeInBytes()
/llvm-project-15.0.7/llvm/lib/Target/AMDGPU/
H A DSIInstrInfo.h1188 const TargetRegisterClass &TRC, in isOfRegClass() argument
1192 return RC == &TRC; in isOfRegClass()
1194 return RC == TRI->getMatchingSuperRegClass(RC, &TRC, P.SubReg); in isOfRegClass()
/llvm-project-15.0.7/clang/lib/Sema/
H A DSemaTemplateVariadic.cpp964 if (Expr *TRC = D.getTrailingRequiresClause()) in containsUnexpandedParameterPacks() local
965 if (TRC->containsUnexpandedParameterPack()) in containsUnexpandedParameterPacks()
H A DSemaLookup.cpp5468 TypoDiagnosticGenerator TDG, TypoRecoveryCallback TRC, CorrectTypoKind Mode, in CorrectTypoDelayed() argument
5495 return createDelayedTypo(std::move(Consumer), std::move(TDG), std::move(TRC), in CorrectTypoDelayed()
5805 TypoRecoveryCallback TRC, in createDelayedTypo() argument
5812 State.RecoveryHandler = std::move(TRC); in createDelayedTypo()
/llvm-project-15.0.7/clang/include/clang/Sema/
H A DDeclSpec.h2502 void setTrailingRequiresClause(Expr *TRC) { in setTrailingRequiresClause() argument
2503 TrailingRequiresClause = TRC; in setTrailingRequiresClause()
2505 SetRangeEnd(TRC->getEndLoc()); in setTrailingRequiresClause()
/llvm-project-15.0.7/llvm/include/llvm/CodeGen/GlobalISel/
H A DMachineIRBuilder.h78 DstOp(const TargetRegisterClass *TRC) : RC(TRC), Ty(DstType::Ty_RC) {} in DstOp() argument
/llvm-project-15.0.7/llvm/lib/Target/AArch64/
H A DAArch64InstrInfo.cpp3205 const TargetRegisterClass *TRC = ::getRegClass(MI, Reg); in isQForm() local
3206 return TRC == &AArch64::FPR128RegClass || in isQForm()
3207 TRC == &AArch64::FPR128_loRegClass; in isQForm()
3224 const TargetRegisterClass *TRC = ::getRegClass(MI, Reg); in isFpOrNEON() local
3225 return TRC == &AArch64::FPR128RegClass || in isFpOrNEON()
3226 TRC == &AArch64::FPR128_loRegClass || in isFpOrNEON()
3227 TRC == &AArch64::FPR64RegClass || in isFpOrNEON()
3228 TRC == &AArch64::FPR64_loRegClass || in isFpOrNEON()
3229 TRC == &AArch64::FPR32RegClass || TRC == &AArch64::FPR16RegClass || in isFpOrNEON()
3230 TRC == &AArch64::FPR8RegClass; in isFpOrNEON()
/llvm-project-15.0.7/llvm/lib/CodeGen/LiveDebugValues/
H A DInstrRefBasedImpl.cpp1226 const TargetRegisterClass *TRC = nullptr; in transferDebugInstrRef() local
1229 TRC = TRCI; in transferDebugInstrRef()
1230 assert(TRC && "Couldn't find target register class?"); in transferDebugInstrRef()
1234 unsigned MainRegSize = TRI->getRegSizeInBits(*TRC); in transferDebugInstrRef()
/llvm-project-15.0.7/clang/lib/AST/
H A DDeclTemplate.cpp241 if (const Expr *TRC = FD->getTrailingRequiresClause()) in getAssociatedConstraints() local
242 AC.push_back(TRC); in getAssociatedConstraints()
/llvm-project-15.0.7/llvm/lib/Target/PowerPC/
H A DPPCMIPeephole.cpp967 const TargetRegisterClass *TRC = MI.getOpcode() == PPC::ADD8 in simplifyCode() local
970 MRI->setRegClass(DominatorReg, TRC); in simplifyCode()
/llvm-project-15.0.7/llvm/lib/Target/Hexagon/
H A DHexagonInstrInfo.cpp2094 const TargetRegisterClass *TRC; in createVR() local
2096 TRC = &Hexagon::PredRegsRegClass; in createVR()
2098 TRC = &Hexagon::IntRegsRegClass; in createVR()
2100 TRC = &Hexagon::DoubleRegsRegClass; in createVR()
2105 Register NewReg = MRI.createVirtualRegister(TRC); in createVR()
/llvm-project-15.0.7/llvm/lib/Target/SystemZ/
H A DSystemZISelDAGToDAG.cpp1718 const TargetRegisterClass *TRC = in SelectInlineAsmMemoryOperand() local
1721 SDValue RC = CurDAG->getTargetConstant(TRC->getID(), DL, MVT::i32); in SelectInlineAsmMemoryOperand()

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